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| MT90868 High Bandwidth Digital Switch Data Sheet Features * * * * * * * * * * * 32,768-channel x 8,192-channel blocking switching between backplane and local streams 8,192-channel x 8,192-channel non-blocking switching for local input and output streams 1,024-channel x 1,024-channel switch between two selected backplane input and output streams Rate conversion between backplane and local streams Accepts ST-BUS streams with data rate of 16.384Mb/s or 32.768Mb/s for backplane port Accepts ST-BUS streams with data rate of 8.192Mb/s for local port Per-stream channel and bit delay for the local input streams Per-stream channel and bit advancement for the local output streams Per-stream bit delay for the backplane input streams Per-stream bit advancement for the backplane output streams Per-channel constant throughput delay BIME VDD_IO VDD_core December 2002 Ordering Information MT90868AG 466 Ball-PBGA -40 to +85 C * * * * Per-channel high impedance output control for local streams Per-channel high impedance or driven-high output control for backplane streams Per-channel message mode for backplane and local output streams Pseudo-Random Binary Sequence (PRBS) pattern generation and testing for local and backplane ports Non-multiplexed microprocessor interface Connection memory block programming for fast device initialization Tristate-control outputs for external drivers on local port RESET ODE * * * VSS (GND) Bit De-multiplexer Mux Output Mux Bit Multiplexer BSTo0-63 Mux Backplane Interface P/S Converter Loopback Data Memory (1,024 channels) Local Connection Memory (8,192 locations) Mux S/P Converter Local Interface P/S Converter Backplane Interface Backplane Data Memories (32,768 channels) Mux BSTi0-63 Output Channel Advancement Buffer LSTo0-63 LCSTo0-3 FP4o FP8o FP16o C4o C8o C16o Local Timing Unit Local Interface S/P Converter Local Data Memories (8,192 channels) Output Mux Backplane Connection Memory (32,768 locations) Mux FP8i Backplane Timing Unit Input Channel Delay Buffer LSTi0-63 C8i APLL Microprocessor Interface and Internal Registers Test Port IC0-IC5 TM1 TM2 SG1 AT1 DT1 DS CS R/W A15-A0 DTA D15-D0 TMS TDi TDo TCK TRST Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. 1 MT90868 * * * Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard 1.8V core supply voltage 3.3V I/O supply voltage with 5V tolerant I/O's Data Sheet Applications * * * * Mediation switches High capacity TDM switching platforms utilizing DS-3/OC-3 rates Central office switches Access equipment Description The MT90868 Digital Switch provides switching capacities of 32,768 x 8,192 channels between backplane and local streams, 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams. The local port has sixty-four input and sixty-four output streams which operate at 8.192Mb/s. The backplane port has sixty-four input and sixty-four output streams which operate at 16.384Mb/s or 32.768Mb/s. The MT90868 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay, high impedance output control for both local and backplane streams and the driven-high backplane output control. 2 Zarlink Semiconductor Inc. Data Sheet MT90868 BSTo BSTo BSTi BSTi BSToBSTo IC3 BSTi BSTi BSTi BSTi LSTo LSTo LSTo LSTo LSTo LSTo LSTo LSTi LSTi LSTo LSTo LSToLSTo LSTo LSTo C C _13 _12 _15 _12 _7 _4 _4 _2 _0 _7 _63 _60 _59 _57 _55 _53 _51 _51 _48 _43 _42 _41 _40 _39 _38 BSTo BSTo BSTi Vss Vdd_ Vss IC4 IC5 IC1 IC2 IC0 LSTo LSToLSTo LSTo LSTo LSTo LSTo LSTo LSTo Vss Vdd_ LSTo LSTo LSTo Vss _37 _36 _35 D D _15 _14 _16 _62 _61 _58 _56 _54 _52 _50 _49 _48 io io BSTi BSTi BSTi Vdd_ E _19 _18 _17 io BSTi BSTi BSTi F _22 _21 _20 Vss BSTo BSTo BSTi Vdd_ G _17 _16 _23 core BSTo BSToBSTo BSTo H _21 _20 _19 _18 Vss BSTo BSTo BSTi BSTi Vdd_ J _22 _23 _25 _24 io BSTo BSTo BSTi BSTi K _25 _24 _27 _26 Vss BSTo BSTo BSTi BSTi Vdd_ L _27 _26 _28 _29 io BSTo BSTo BSTi BSTi Vdd_ M _29 _28 _30 _31 core BSTo BSTo BSTi BSTi N _30 _31 _33 _32 Vss BSTo BSTo BSTi BSTi P _33 _32 _34 _35 Vss BSTo BSTo BSTi BSTi Vdd_ R _35 _34 _37 _36 core BSTo BSTo BSTi BSTi Vdd_ T _37 _36 _39 _38 io U V W Y Vdd_ Vdd_ Vss Vdd_ Vss Vdd_ Vdd_ Vdd_ Vdd_Vdd_ Vss Vss core io Vss io Vss core core io io core R 1 2 3 BSTo BSTo BSTi A _8 _9 _13 BSTo BSTo BSTi B _10 _11 _14 1 4 6 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 7 9 BSTi BSTi BSToBSToBSTo BSTi BSTi TDi TCK TDo LSTi LSTi LSTi LSTi LSTi LSTi LSTi LSTo LSTo LSTi LSTi LSTi LSTi _62 _61 _59 _57 _54 _53 _50 _47 _46 _47 _46 _44 _42 A _6 _3 _11 _9 _6 _3 _1 BSTi BSTi BSToBSTo BSTo BSTi BSTi _5 _1 TRSTTMS _10 _8 _5 _2 _0 LSTi LSTi LSTi LSTi LSTi LSTi LSTi LSTo LSTo LSTi LSTi LSTi LSTi _63 _60 _58 _56 _55 _52 _49 _45 _44 _45 _43 _41 _40 B es et Vdd_ LSTo LSTo LSTo io _34 _33 _32 E LSTi Vss _39 Vdd_ LSTi core _36 Vss Vdd_ LSTo _31 io Vdd_LSTo LSTo core _30 _29 LSTi _38 LSTi _35 LSTi _33 LSTi _31 LSTi _37 F LSTi _34 G LSTi H _32 LSTi _28 J Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss LSToLSTo LSTo LSTi LSTi _28 _27 _26 _30 _27 K Vdd_LSTo LSTo LSTi LSTi io _24 _25 _29 _26 L Vdd_LSTo LSTo LSTi LSTi M core _23 _22 _25 _24 Vdd_LSTo LSTo LSTi LSTi N io _21 _20 _23 _20 Vss LSTo LSTo _18 _19 Vdd_LSTo LSTo Core _17 _16 Vdd_LSTo LSTo io _15 _14 LSTo LSTo Vss _12 _13 Vdd_LSTo LSTo core _8 _11 LSTo Vss Vdd _10 io Vdd_LSTo core _9 Vss LSTi _22 LSTi _21 LSTi _17 LSTi _15 LSTi _14 LSTi _13 LSTi _9 LSTi P _19 LSTi _18 R LSTi T _16 LSTi _12 U LSTi _11 V LSTi _10 W LSTi Y _8 BSTo BSTo _38 _39 BSTo BSTo _41 _40 BSTo BSTo _43 _42 BSTo BSTo _45 _44 BSTi BSTi _40 _41 Vss BSTi BSTi Vdd_ io _42 _45 BSTi BSTi Vss _43 _47 BSTi Vdd_ _44 core TOP VIEW BSTo BSTo BSTi AA _46 _47 _46 Vss BSTi BSTi BSTi Vdd_ AB _48 _49 _50 io AC LSTo LSToLSTo _7 _6 _5 AA Vss Vdd_ Vss Vdd_ Vdd_ Vdd_ Vdd_ Vdd_ Vss io Vss io Vss core Vss core core io A4 A8 A7 A6 A5 Vdd_ A10 Core A1 A2 A3 A9 A14 A11 A15 D3 D2 D1 D0 16 Vdd_LSTo LSTo LSTo io _4 _3 _2 AB LSTi AC _6 LSTi AD _4 LSTi AE _2 BSTi BSTi BSTi Vdd_ Vdd_ Vdd_ _51 _52 _53 core io Vss core FP8i BSTi BSTi BSTi BSTi BSTi BSTi AD _54 _55 _57 _56 _58 _62 ODE BIME BSTo BSToBSTo BSTo BSTi BSTi BSTo BSTo AE _48 _50 _53 _54 _59 _63 _56 _59 BSTo BSTo DT1 C8i CLK A0 A13 _63 _62 BYPS BSTo BSTo BSToBSTo BSTi BSTi BSTo BSTo BSTo BSTo SG1 TM2 TM1 AT1 A12 AF _49 _51 _52 _55 _60 _61 _57 _58 _60 _61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vdd_ LSTo LSTi D7 D11 D15 core Vss Vss Vss _1 _7 LCS LCS LCS LCS LSTo LSTi D6 D10 D14 To_0 To_1 To_2 To_3 _0 _5 LSTi D5 D9 D13 DTA DS C4o C8o C16o _3 D4 17 D8 D12 R/W CS 18 19 20 21 FP 4o 22 FP FP LSTi LSTi AF _1 8o 16o _0 23 24 25 26 1 - A1 corner is identified by metallized markings. Figure 2 - 35mm x 35mm PBGA (JEDEC MO-151) Pinout Zarlink Semiconductor Inc. 3 MT90868 Ball Signal Assignment Ball Number Signal Name Ball Number Signal Name Ball Number Data Sheet Signal Name A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 LSTi42 BSTo10 BSTo11 BSTi14 BSTi10 BSTi8 BSTo5 BSTo2 BSTo0 BSTi5 BSTi1 TRST TMS RESET LSTi63 LSTi60 LSTi58 LSTi56 LSTi55 LSTi52 LSTi49 LSTo45 LSTo44 LSTi45 LSTi43 LSTi41 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 LSTi40 BSTo13 BSTo12 BSTi15 BSTi12 BSTo7 BSTo4 IC3 BSTi7 BSTi4 BSTi2 BSTi0 LSTo63 LSTo60 LSTo59 LSTo57 LSTo55 LSTo53 LSTo51 LSTi51 LSTi48 LSTo43 LSTo42 LSTo41 LSTo40 LSTo39 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 BSTo8 BSTo9 BSTi13 BSTi11 BSTi9 BSTo6 BSTo3 BSTo1 BSTi6 BSTi3 TDi TCK TDo LSTi62 LSTi61 LSTi59 LSTi57 LSTi54 LSTi53 LSTi50 LSTo47 LSTo46 LSTi47 LSTi46 LSTi44 4 Zarlink Semiconductor Inc. Data Sheet Ball Number Signal Name Ball Number Signal Name Ball Number MT90868 Signal Name C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 LSTo38 BSTo15 BSTo14 BSTi16 GND VDD_IO GND IC4 IC5 IC1 IC2 IC0 LSTo62 LSTo61 LSTo58 LSTo56 LSTo54 LSTo52 LSTo50 LSTo49 LSTo48 GND VDD_IO GND LSTo37 LSTo36 D26 E1 E2 E3 E4 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E23 E24 E25 E26 F1 F2 F3 LSTo35 BSTi19 BSTi18 BSTi17 VDD_IO VDD_CORE GND VDD_IO GND VDD_IO VDD_CORE GND GND VDD_CORE VDD_IO GND VDD_IO GND VDD_CORE VDD_IO LSTo34 LSTo33 LSTo32 BSTi22 BSTi21 BSTi20 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 GND GND LSTi39 LSTi38 LSTi37 BSTo17 BSTo16 BSTi23 VDD_CORE VDD_CORE LSTi36 LSTi35 LSTi34 BSTo21 BSTo20 BSTo19 BSTo18 GND GND VDD_IO LSTo31 LSTi33 LSTi32 BSTo22 BSTo23 BSTi25 Zarlink Semiconductor Inc. 5 MT90868 Ball Number Signal Name Ball Number Signal Name Ball Number Data Sheet Signal Name J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K10 K11 K12 K13 K14 K15 K16 K17 K22 K23 K24 K25 K26 L1 BSTi24 VDD_IO VDD_CORE LSTo30 LSTo29 LSTi31 LSTi28 BSTo25 BSTo24 BSTi27 BSTi26 GND GND GND GND GND GND GND GND GND LSTo28 LSTo27 LSTo26 LSTi30 LSTi27 BSTo27 L2 L3 L4 L5 L10 L11 L12 L13 L14 L15 L16 L17 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M10 M11 M12 M13 BSTo26 BSTi28 BSTi29 VDD_IO GND GND GND GND GND GND GND GND VDD_IO LSTo24 LSTo25 LSTi29 LSTi26 BSTo29 BSTo28 BSTi30 BSTi31 VDD_CORE GND GND GND GND M14 M15 M16 M17 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N10 N11 N12 N13 N14 N15 N16 N17 N22 N23 N24 N25 GND GND GND GND VDD_CORE LSTo23 LSTo22 LSTi25 LSTi24 BSTo30 BSTo31 BSTi33 BSTi32 GND GND GND GND GND GND GND GND GND VDD_IO LSTo21 LSTo20 LSTi23 6 Zarlink Semiconductor Inc. Data Sheet Ball Number Signal Name Ball Number Signal Name Ball Number MT90868 Signal Name N26 P1 P2 P3 P4 P5 P10 P11 P12 P13 P14 P15 P16 P17 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R10 R11 LSTi20 BSTo33 BSTo32 BSTi34 BSTi35 GND GND GND GND GND GND GND GND GND GND LSTo18 LSTo19 LSTi22 LSTi19 BSTo35 BSTo34 BSTi37 BSTi36 VDD_CORE GND GND R12 R13 R14 R15 R16 R17 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 T15 T16 T17 T22 T23 GND GND GND GND GND GND VDD_CORE LSTo17 LSTo16 LSTi21 LSTi18 BSTo37 BSTo36 BSTi39 BSTi38 VDD_IO GND GND GND GND GND GND GND GND VDD_IO LSTo15 T24 T25 T26 U1 U2 U3 U4 U5 U10 U11 U12 U13 U14 U15 U16 U17 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 LSTo14 LSTi17 LSTi16 BSTo38 BSTo39 BSTi40 BSTi41 GND GND GND GND GND GND GND GND GND GND LSTo12 LSTo13 LSTi15 LSTi12 BSTo41 BSTo40 BSTi42 BSTi45 VDD_IO Zarlink Semiconductor Inc. 7 MT90868 Ball Number Signal Name Ball Number Signal Name Ball Number Data Sheet Signal Name V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 VDD_CORE LSTo8 LSTo11 LSTi14 LSTi11 BSTo43 BSTo42 BSTi43 BSTi47 GND GND VDD_IO LSTo10 LSTi13 LSTi10 BSTo45 BSTo44 BSTi44 VDD_CORE VDD_CORE LSTo9 LSTi9 LSTi8 BSTo46 BSTo47 BSTi46 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB23 AB24 AB25 AB26 AC1 GND GND LSTo7 LSTo6 LSTo5 BSTi48 BSTi49 BSTi50 VDD_IO GND VDD_IO GND VDD_CORE GND VDD_CORE GND VDD_CORE VDD_IO GND VDD_IO GND VDD_IO LSTo4 LSTo3 LSTo2 BSTi51 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 BSTi52 BSTi53 VDD_CORE VDD_IO GND VDD_CORE FP8i A4 A7 A5 VDD_CORE A10 A9 A14 D3 D7 D11 D15 VDD_CORE GND GND GND LSTo1 LSTi7 LSTi6 BSTi54 8 Zarlink Semiconductor Inc. Data Sheet Ball Number Signal Name Ball Number Signal Name Ball Number MT90868 Signal Name AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 BSTi55 BSTi57 BSTi56 BSTi58 BSTi62 ODE BIME A8 A6 A1 A2 A3 A11 A15 D2 D6 D10 D14 LCSTo0 LCSTo1 LCSTo2 LCSTo3 LSTo0 LSTi5 LSTi4 BSTo48 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 BSTo50 BSTo53 BSTo54 BSTi59 BSTi63 BSTo56 BSTo59 BSTo63 BSTo62 DT1 C8i CLKBYPS A0 A13 D1 D5 D9 D13 DTA DS C4o C8o C16o LSTi3 LSTi2 BSTo49 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 BSTo51 BSTo52 BSTo55 BSTi60 BSTi61 BSTo57 BSTo58 BSTO60 BSTO61 SG1 TM2 TM1 AT1 A12 D0 D4 D8 D12 R/W CS FP4o FP8o FP16o LSTi0 LSTi1 Zarlink Semiconductor Inc. 9 MT90868 Pin Description PBGA Ball Number E12, E15, E20, E7, G23, G4, J22, M22, M5, R22, R5, V22, Y23, Y4, AB11, AB13, AB15, AC20, AC4, AC7. D22, D5, E11, E16, E18, E23, E4, E9, H23, J5, L22, L5, N22, T22, T5, V5, W23, AB16, AB18, AB23, AB4, AB9, AC5. M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, N5, P10, P11, P12, P13, P14, P15, P16, P17, P22, P5, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17, U22, U5, W22, W5. C11, B10, C10, A10, C9, B9, A9, C8, B5, A5, B4, A4, C4, A3, B3, C3, D3, E3, E2, E1, F3, F2, F1, G3, J4, J3, K4, K3, L3, L4, M3, M4, N4, N3, P3, P4, R4, R3, T4, T3, U3, U4, V3, W3, Y3, V4, AA3, W4, AB1, AB2, AB3, AC1, AC2, AC3, AD1, AD2, AD4, AD3, AD5, AE5, AF5, AF6, AD6, AE6. B8, A8, B7, A7, C6, B6, A6, C5, A1, A2, B1, B2, C2, C1, D2, D1, G2, G1, H4, H3, H2, H1, J1, J2, K2, K1, L2, L1, M2, M1, N1, N2, P2, P1, R2, R1, T2, T1, U1, U2, V2, V1, W2, W1, Y2, Y1, AA1, AA2, AE1, AF1, AE2, AF2, AF3, AE3, AE4, AF4, AE7, AF7, AF8, AE8, AF9, AF10, AE10, AE9. AC8 Name VDD_CORE Description Data Sheet Power Supply for Core Logic Circuits: +1.8V VDD_IO Power Supply for Pads: +3.3V. The VDD_IO supply has to be either established before the power up of the VDD_CORE supply or the VDD_CORE should not "lead" the VDD_IO by more than 0.3V. Ground Vss (GND) BSTi0 - 63 Backplane Serial Input Streams 0 to 63 (5V Tolerant Inputs): In 16Mb/s mode, these pins accept serial TDM data streams at 16.384 Mb/s with 256 channels per stream. In 32Mb/s mode, these pins accept serial TDM data streams at 32.768 Mb/s with 512 channels per stream. BSTo0 - 63 Backplane Serial Output Streams 0 to 63 (5V Tolerant Three-state Outputs): In 16Mb/s mode, these pins have data rate of 16.384 Mb/s with 256 channels per stream. In 32Mb/s mode, these pins have data rate of 32.768 Mb/s with 512 channels per stream. FP8i Frame Pulse Input (5V Tolerant Input): This pin accepts the backplane frame pulse which is low for 122ns (one 8.192MHz period) at the frame boundary. The frame pulse frequency is 8kHz. Master Clock Input (5V Tolerant Input): This pin accepts an 8.192MHz clock. The clock falling edge is aligned with the backplane frame boundary. This input must be provided for any function to operate. APLL Bypass clock (5V Tolerant Input): This pin accepts a 131.072MHz clock for device testing purpose. In normal operation, this input MUST be low. AE12 C8i AE13 CLKBYPS 10 Zarlink Semiconductor Inc. Data Sheet Pin Description (continued) PBGA Ball Number AF13 AF12 AF11 AF14 Name TM1 TM2 SG1 AT1 Description MT90868 APLL Test Pin 1 (3.3V Tolerant Input): Used for APLL testing only. In normal operation, this input MUST be low. APLL Test Pin 2 (3.3V Tolerant Input): Used for APLL testing only. In normal operation, this input MUST be low. APLL Test Control (3.3V Tolerant Input): Used for APLL testing only. In normal operation, this input MUST be low. Analog Test Access (3.3V Tolerant I/O): Used for APLL testing only. This pin is pulled low by an internal pull-down resistor. No connection for normal operation. Digital Test Access (3.3V Output): Used for APLL testing only. No connect for normal operation. Chip Select (5V Tolerant Input): Active low input used by the microprocessor to enable the microprocessor port access. Data Strobe (5V Tolerant Input): This active low input works in conjunction with CS to enable the microprocessor port read and write operations. Read/Write (5V Tolerant Input): This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Address 0 - 15 (5V Tolerant Inputs): These pins form the 16-bit address bus of the microprocessor port. AE11 AF21 DT1 CS AE21 DS AF20 R/W AE14, AD11, AD12, AD13, AC9, AC11, AD10, AC10, AD9, AC14, AC13, AD14, AF15, AE15, AC15, AD15. AF16, AE16, AD16, AC16, AF17, AE17, AD17, AC17, AF18, AE18, AD18, AC18, AF19, AE19, AD19, AC19. AE20 A0 - A15 D0 - D15 Data Bus 0 - 15 (5V Tolerant I/Os): These pins form the 16-bit data bus of the microprocessor port. DTA Data Transfer Acknowledgment (5V Tolerant Output): This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold at HIGH level. Test Mode Select (5V Tolerant Input with internal pullup): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pullup resistor when it is not driven. Test Clock (5V Tolerant Input): Provides the clock to the JTAG test logic. Test Serial Data In (5V Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. B12 TMS A12 A11 TCK TDi Zarlink Semiconductor Inc. 11 MT90868 Pin Description (continued) PBGA Ball Number A13 Name TDo Description Data Sheet Test Serial Data Out (5V Tolerant Three-state Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Test Reset (5V Tolerant Input with internal pull-up): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. Device Reset (5V Tolerant Input with internal pull-up): This input (active LOW) puts the device in its reset state that disables the LSTo0 - 63 driver and drives the BSTo0 63, LCSTo-3 outputs to high. It also clears the device registers and internal counters. To ensure proper reset action, the reset pin must be held low for longer than 500ns. A delay of 100s must also be applied before the first microprocessor access is performed after the RESET pin is set high, this delay is required for the initialization of the APLL. In normal operation, this input MUST be connected to ground. In normal operation, this input MUST be connected to ground. In normal operation, this input MUST be connected to ground. In normal operation, this input MUST be connected to ground. In normal operation, this input MUST be connected to ground. In normal operation, this input MUST be connected to ground. Local Serial Input Streams 0 to 63 (5V Tolerant Inputs): These inputs accept data rates of 8.192 Mb/s with 128 channels per stream. B11 TRST B13 RESET D11 D9 D10 C7 D7 D8 AF25, AF26, AE26, AE25, AD26, AD25, AC26, AC25, Y26, Y25, W26, V26, U26, W25, V25, U25,T26,T25, R26, P26, N26, R25, P25, N25, M26, M25, L26, K26, J26, L25, K25, J25, H26, H25, G26, G25, G24, F26, F25, F24, B26, B25, A26, B24, A25, B23, A24, A23, C20, B20, A20, C19, B19, A19, A18, B18, B17, A17, B16, A16, B15, A15, A14, B14. IC0 IC1 IC2 IC3 IC4 IC5 LSTi0 - 63 12 Zarlink Semiconductor Inc. Data Sheet Pin Description (continued) PBGA Ball Number AD24, AC24, AB26, AB25, AB24, AA26, AA25, AA24, V23, Y24, W24, V24, U23, U24, T24, T23, R24, R23, P23, P24, N24, N23, M24, M23, L23, L24, K24, K23, K22, J24, J23, H24, E26, E25, E24, D26, D25, D24, C26, C25, C24, C23, C22, C21, B22, B21, A22, A21, D20, D19, D18, C18, D17, C17, D16, C16, D15, C15, D14, C14, C13, D13, D12, C12 AE24 Name LSTo0 - 63 Description MT90868 Local Serial Output Streams 0 to 63 (5V Tolerant Three-state Outputs): These outputs have data rates of 8.192 Mb/s with 128 channels per stream. C16o Local C16o Clock (3.3V Three-state Output): A 16.384MHz clock output. The clock falling edge is aligned with the local frame boundary. Local C8o Clock (3.3V Three-state Output): A 8.192MHz clock output. The clock falling edge is aligned with the local frame boundary. Local C4o Clock (3.3V Three-state Output): A 4.096MHz clock output. The clock falling edge is aligned with the local frame boundary. Local ST-Bus Frame Pulse Output (3.3V Three-state Output): Local port ST-BUS frame pulse output which is low for 61ns at the frame boundary. Its frequency is 8KHz. Local CT-Bus Frame Pulse Output (3.3V Three-state Output): Local port ST-BUS frame pulse output which is low for 122ns at the frame boundary. Its frequency is 8KHz. Local ST-Bus Frame Pulse Output (3.3V Three-state Output): Local port ST-BUS frame pulse output which is low for 244ns at the frame boundary. Its frequency is 8KHz. Local Tristate Control Streams 0 to 3 (3.3V Three-state Outputs): These pins are used for per-channel external tristate control of the local output streams. The bit rate is 16.384MHz. When RESET pin or ODE pin is low, the LCSTo0 - 3 are driven high. Output Drive Enable (5V Tolerant Input): This is the asynchronously output enable control for the BSTo0 - 63 and LSTo0 - 63 serial outputs. When it is high, the BSTo0 - 63, LSTo0 - 63 and LCSTo0-3 are enabled. When it is low, the BSTo0 - 63 are tristated or driven high, the LSTo0 - 63 are tristated and the LCSTo0 - 3 are driven high. AE23 C8o AE22 C4o AF24 FP16o AF23 FP8o AF22 FP4o AD20- AD23 LCSTo0 - 3 AD7 ODE Zarlink Semiconductor Inc. 13 MT90868 Pin Description (continued) PBGA Ball Number AD8 Name BIME Description Data Sheet Bit Interleaving Mode Enable (5V Tolerant Input with internal pull down): When BIME and the BMS bit in the control register are both high, the bit interleaving mode is enabled. See Figure 26 for the bit interleaving mode timing diagram. When it is low, the bit interleaving mode is disabled and the BMS bit in the control register selects the 16Mb/s or 32Mb/s mode for the backplane streams. 14 Zarlink Semiconductor Inc. Data Sheet 1.0 Device Overview MT90868 The MT90868 can switch up to 32,768 x 8,192 channels while providing a rate conversion capability. It is designed to switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local switching applications. The device maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel basis. The backplane interface can operate at 16.384Mb/s or 32.768Mb/s on ST-BUS and is arranged in 125s wide frames that contain 256 or 512 channels respectively. A built-in rate conversion circuit allows users to interface between backplane and local interfaces which operates at 8.192Mb/s. By using Zarlink's message mode capability, the microprocessor can access input and output time slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other STBUS devices. 1.1 Functional Description A Functional Block Diagram of the MT90868 is shown in Figure 1. It is designed to interface ST-BUS serial streams from a backplane source and ST-BUS serial streams from a local source. 1.2 Frame Alignment Timing In the ST-BUS mode, the C8i pin accepts a 8.192MHz clock for the frame pulse alignment. The FP8i is a 8kHz frame pulse signal which goes low at the frame boundary for 122ns. The frame boundary is defined by the falling edge of the C8i clock during the low cycle of the frame pulse. Figure 3 shows the backplane port timing diagram with the data rate of 16Mb/s and 32Mb/s. The BFP8C bit in the block programming mode register (BPR) allows the device to accept different frame pulse formats. If the BFP8C bit in the block programming register is low, the device accepts a negative frame pulse. If the BFP8C bit is high, the device accepts a positive frame pulse as described in Figure 3. The device accepts the backplane frame pulse input and generates the local frame pulse outputs. When the 16Mb/s or 32 Mb/s mode is selected for the backplane port, the delay between the backplane and local frame pulse signals is two 16Mb/s or 32Mb/s backplane channels plus 10 cycles of C8i respectively. Figures 4 and 5 show the backplane and local frame pulse alignment for the 16Mb/s and the 32Mb/s timing mode respectively. 1.3 Local Interface Output Timing The local frame pulses, FP4o, FP8o and FP16o are 8kHz output signals that have a pulse width of 244ns, 122ns and 61ns respectively at the frame boundary. The frame boundary is defined by the falling edge of the C8o output clock during the low cycle of the frame pulse FP8o. At the frame boundary, the falling edges of the C4o and C16o output clocks are aligned with the falling edge of the C8o output clock. In addition, the C8o clock can be inverted by programming the C8C bit to high in the BPR register. When the LFP4C, LFP8C and LFP16C bits are programmed to high in the BPR register, the device will provide positive frame pulse for the FP4o, FP8o and FP16o outputs. The local port timing diagram is shown in Figure 6. Zarlink Semiconductor Inc. 15 MT90868 FP8i (8kHz) BFP8C = 0 FP8i BFP8C = 1 C8i (8.192MHz) Channel 0 Channel 255 2 1 0 6 5 4 3 2 1 Data Sheet . BSTi/BSTo0-63 (16Mb/s) BSTi/BSTo0-63 (32Mb/s) 1 0 7 6 5 4 3 0 7 Channel 0 Channel 1 Channel 510 Channel 511 32107654321076543210 65432107654321076 Figure 3 - Backplane Port Timing Diagram for 16Mb/s and 32Mb/s modes Two (16Mb/s) channels + Ten C8i Cycles FP8i C8i BSTi/BSTo0-633 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 (16Mb/s) FP8o C8o LSTi/LSTo0-63 (8Mb/s) Channel 125 2 1 0 7 6 5 Channel 126 4 3 2 1 0 7 6 5 Channel 127 4 3 2 1 0 Ch0 7 Ch255 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Figure 4 - Backplane and Local Frame Pulse Alignment, Backplane Data Rate is 16Mb/s Two (32Mb/s) channels + Ten C8i Cycles FP8i C8i BSTi/BSTo0-63 (32Mb/s) FP8o C8o LSTi/LSTo0-63 (8Mb/s) Channel 126 6 5 4 3 2 1 0 7 6 Channel 127 5 4 3 2 1 0 7 6 Channel 0 5 4 3 Ch 511 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 1 Figure 5 - Backplane and Local Frame Pulse Alignment, Backplane Date Rate is 32Mb/s 16 Zarlink Semiconductor Inc. Data Sheet FP4o (8kHz) LFP4C = 0 FP4o LFP4C = 1 C4o (4.096MHz) MT90868 FP8o LFP8C = 0 FP8o LFP8C = 1 C8o (8.192MHz) C8C=0 C8o (8.192MHz) C8C=1 FP16o LFP16C = 0 FP16o LFP16C = 1 C16o (16.384MHz) Channel 0 Channel 1 Channel 126 Channel 127 LSTi/LSTo0-63 (8Mb/s) 32107654321076543210 65432107654321076 Figure 6 - Local Port Timing Diagram Zarlink Semiconductor Inc. 17 MT90868 2.0 Switching Configuration Data Sheet The MT90868 has two operation modes at different data rates for the backplane interface and one operation mode for the local interface. The two operation modes for the backplane interface can be selected via the backplane mode selection bit (BMS) in the Control Register (CR). 2.1 Backplane Interface The backplane interface can be programmed to accept data streams of 16Mb/s or 32Mb/s. When BMS bit of the CR register is low, the 16Mb/s mode is enabled, BSTi0-63 and BSTo0-63 have a data rate of 16.384Mb/s. When BMS = 1, the 32Mb/s mode is enabled, BSTi0-63 and BSTo0-63 have a data rate of 32.768Mb/s. Table 1 describes the data rates and mode selections for the backplane interface. 2.2 Local Interface The local interface has one mode of operation which can only operate at the data rate of 8.192Mb/s. 2.3 Output Bit Advancement Selection The device allows users to advance individual backplane or local output streams with respect to the frame boundary. This feature is useful in compensating variable output delays caused by various output loading conditions. Each output stream can have its own advancement value programmed by the output advancement registers. The backplane output advancement registers (BOAR0 to BOAR7) are used to program the backplane output advancement. The local output advancement registers (LOAR0 to LOAR7) are used to program the local output advancement. See Tables 17 and Table 19 for the descriptions of the LOAR and BOAR registers. Possible adjustment for local is -1/8, -1/4 or -3/8 bit and the resolution is 1/8 bit (or 1/8 of C8o cycle). For backplane, the possible adjustment is -1/4, -1/2 or -3/4 bit when the output data rate is 16.384Mb/s. When the backplane data rate is 32.768Mb/s, the possible adjustment is -1/2, -1 or -1 1/2 bit. For both data rates, the resolution is 1/8 of C8i cycle. The advancement is independent of the output data rate. Figures 7, 8 and 9 describe the details of the output advancement programming for the local and the backplane interfaces respectively. 2.4 Input Bit Delay Selection The MT90868 input bit delay features allow users to have more flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on PCM highways which are connected to the switch matrix cards. Each input data stream can have its own input bit delay value programmed by the input delay registers. The local input delay registers (LIDR0 - LIDR21) are used to program the local input delay. The backplane input delay registers (BIDR0 - BIDR21) are used to program the backplane input delay. See Tables 8, 12 and Tables 14, 15 for the descriptions of the LIDR and BIDR registers. BMS bit of the Control Register 0 1 Modes 16.384Mb/s 32.768Mb/s Backplane Interface BSTi0 - 63 and BSTo0 - 63 BSTi0 - 63 and BSTo0 - 63 Table 1 - Mode Selection for Backplane Streams 18 Zarlink Semiconductor Inc. Data Sheet FP8o C8o Ch127 Ch0 Bit 0 Bit Advancement, -1/8 Ch127 Bit 1 Bit 0 Bit Advancement, -1/4 Ch127 Bit 7 Bit 7 Bit 6 MT90868 LSToX Bit Advancement = 0 (Default) LSToX Bit 1 Ch0 Bit 6 Bit Advancement = -1/8 LSToX Ch0 Bit 7 Bit 6 Bit 1 Bit 0 Bit Advancement, -3/8 Ch127 Bit Advancement = -1/4 Ch0 Bit 7 Bit 6 LSToX Bit Advancement = -3/8 Bit 1 Bit 0 Figure 7 - Local Output Advancement Timing Diagram when the Data Rate is 8Mb/s Possible adjustment of the local input data streams, LSTi0 - LSTi63 is up to 7 3/4 bits. The resolution is 1/4 bit or 1/4 C8o cycle. For backplane, the possible adjustment of the input data streams, BSTi0 - BSTi63 is up to 7 3/4 bits with a resolution of 1/4 bit (or 1/8 C8i clock cycle) when the input data rate is 16.384Mb/s. When the input data rate is 32.768Mb/s, the possible adjustment is up to 7 1/2 bits with a resolution of 1/2 bit (or 1/8 C8i clock cycle). Figures 10, 11 and 12 describe the details of the input bit delay programming for the local and the backplane interfaces respectively. FP8i C8i BSToX (16.384Mb/s) Bit advancement = 0 (Default) BSToX Bit Advancement = -1/4 Ch255 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Ch0 Bit 5 Bit 4 Bit Advancement, -1/4 Ch255 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Ch0 Bit 5 Bit 4 Bit Advancement, -1/2 Ch255 Ch0 Bit 7 Bit 6 Bit 5 Bit 4 BSToX Bit Advancement = -1/2 Bit 2 Bit 1 Bit 0 Bit Advancement, -3/4 Ch255 Ch0 Bit 7 Bit 6 Bit 5 Bit 4 BSToX Bit Advancement = -3/4 Bit 2 Bit 1 Bit 0 Figure 8 - Backplane Output Advancement Timing Diagram when the Data Rate is 16Mb/s Zarlink Semiconductor Inc. 19 MT90868 Data Sheet FP8i C8i BSToX (32.768Mb/s) Bit Advancement = 0 (Default) BSToX Bit Advancement = -1/2 Ch511 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Ch0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Advancement, -1/2 Ch511 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Ch0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Advancement, -1 Ch511 Ch0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSToX Bit Advancement = -1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Advancement, -1 1/2 Ch511 Ch0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSToX Bit Advancement = -1 1/2 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 9 - Backplane Output Advancement Timing Diagram when the Data Rate is 32Mb/s FP8o C8o Ch127 Ch0 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 4 LSTiX Bit Delay = 0 (Default) LSTiX Bit Delay = 1/4 3 2 Bit Delay, 1/4 Ch127 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4 Bit Delay, 1/2 LSTiX Bit Delay = 1/2 Ch127 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4 Bit Delay, 3/4 LSTiX Bit Delay = 3/4 Ch127 3 2 1 0 7 6 Bit Delay, 1 Ch127 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4 Ch0 2 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 LSTiX Bit Delay = 1 3 LSTiX Bit Delay = 7 1/2 Ch126 2 1 0 7 6 5 Ch127 4 3 2 1 0 7 Bit Delay, 7 1/2 Ch0 6 5 4 LSTiX Bit Delay = 7 3/4 Ch126 2 1 0 7 6 5 Ch127 4 3 2 1 0 7 Bit Delay, 7 3/4 Ch0 6 5 4 Figure 10 - Local Input Bit Delay Timing Diagram (The Data Rate is 8Mb/s) 20 Zarlink Semiconductor Inc. Data Sheet MT90868 FP8i (8kHz) C8i (8.192MHz) BSTiX (16Mb/s) Bit Delay = 0 Default 1 0 7 6 5 4 Ch 0 3 2 1 0 7 6 5 Ch1 4 3 2 1 0 7 Bit Delay, 1/2 Ch0 Ch1 2 1 0 7 6 5 4 3 2 1 0 7 0 7 6 5 4 3 BSTiX Bit Delay = 1/2 1 Bit Delay, 2 Ch0 4 3 2 1 0 7 6 5 Ch1 4 3 2 1 BSTiX Bit Delay = 2 3 2 1 0 7 6 5 Figure 11 - Backplane Input Bit Delay Timing Diagram when the Data Rate is 16Mb/s FP8i (8kHz) C8i (8.192MHz) Ch0 Ch1 Ch2 Ch3 BSTiX (32Mb/s) Bit Delay = 0 Default BSTiX Bit Delay = 1/2 321076543210765432107654321076543210 Bit Delay, 1/2 Ch0 Ch1 Ch2 Ch3 321076543210765432107654321076543210 Bit Delay, 1 Ch0 BSTiX Bit Delay = 1 Ch1 Ch2 Ch3 4321076543210 765432107 6543210 7654321 Figure 12 - Backplane Input Bit Delay Timing Diagram when the Data Rate is 32Mb/s 2.5 Local Input Channel Delay and Local Channel Output Advancement The MT90868 provides users with the capability of programming the local input channel delay and the local output channel advancement. The local input channel delay programming allows all local input streams to have a different frame boundary with respect to the local frame pulse (F8o). It is enabled when the LICDEN bit in the control register (CR) is high. The local input channel delay registers (LICDR0 - LICDR31) allows the users to delay the input channel from 0 to 127 channel for every local input stream. Figure 13 describes the local channel delay timing with different delay values. The local output channel advancement programming allows all local output streams to have a different frame boundary with respect to the local frame pulse (F8o). It is enabled when the LOCAEN bit in the CR register is set to high. The local output channel advancement registers (LOCAR0 - LOCAR31) allows the users to advance the output channel from 0 to 127 channels for every local output stream. Figure 14 describes the local channel output advancement timing with different channel advancement values. Zarlink Semiconductor Inc. 21 MT90868 FP8o C8o Ch 0 Ch 1 Ch126 Ch127 Data Sheet LSTiX Channel Delay = 0 (Default) 32107654321076543210 Delay = 1 Ch127 65432107654321076 Ch 0 Ch125 Ch126 LSTiX Channel Delay = 1 32107654321076543210 65432107654321076 Ch126 Delay = 2 Ch127 Ch0 Ch125 7654321076 LSTiX Channel Delay = 2 Note: X = 0 to 63 3210765432107654321076543210 Figure 13 - Local Input Channel Delay Timing Diagram FP8o C8o Ch 0 Ch 1 Ch126 Ch127 LSToY Channel Advance =0 (Default) 32107654321076543210 65432107654321076 Advance = 1 Ch0 Ch1 Ch2 Ch127 LSToY Channel Advance = 1 32107654321076543210 65432107654321076 Ch2 Ch3 Ch0 Advance = 2 Ch1 LSToY Channel Advance = 2 32107654321076543210 76543210 7654321076 Note: Y = 0 to 63 Figure 14 - Local Output Channel Advancement Timing Diagram 2.6 Memory Block Programming The block programming register (BPR) provides users with the capability of initializing the local and backplane connection memories in two frames. The local connection memory is partitioned into local connection memory high (LCMH) and the local connection memory low (LCML). Bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in bit 4 - bit 6 of the BPR register. Bit 15 of every LCML location and bit 0 - bit 1 of every LCMH location will be programmed with the pattern stored in bits 1 to 3 of the BPR register. The other bit positions of the backplane connection memory, the local connection memory low and all bits of the local connection memory high are loaded with zeros. See Figure 15 for the connection memory contents when the device is in the block programming mode. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register to 22 Zarlink Semiconductor Inc. Data Sheet MT90868 high. When the block programming enable (BPE) bit of the BPR register is set to high, the block programming data will be loaded into bits 13 to 15 of every backplane connection memory location and bits 15 of every local connection memory low and bit 0 to bit 1 of every local connection memory high location. The other connection memory bits are loaded with zeros. It takes two frames (250s) to allow the backplane and local connection memories to be loaded. Upon the completion of the memory block programming, the device resets the BPE bit to low to indicating that the process is finished. See Table 6 for the bit assignment of the BPR register. 15 BBPD2 14 BBPD1 13 BBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Backplane Connection Memory (BCM) 15 LBPD0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Local Connection Memory Low (LCML) 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 LBPD2 0 LBPD1 Local Connection Memory High (LCMH) Figure 15 - Block Programming Data in the Connection Memories Zarlink Semiconductor Inc. 23 MT90868 3.0 Switching Paths Data Sheet The MT90868 provides users with four switching paths, namely "backplane-to-local", "local-to-backplane", "backplane-to-backplane" and "local-to-local". The switching configuration is controlled by programming the local connection and the backplane connection memories. The "backplane-to-local" switching path allows the device to perform data switching between the backplane input port and the local output port among 32,768 backplane input channels and 8,192 local output channels. The local connection memory determines the switching configurations. See Table 30 and Table 31 for the details. The "local-to-backplane" switching path allows users to perform data switching between the local input port and the backplane output port among 8,192 local input channels and 16,380 or 32,760 backplane output channels when operated in the 16Mb/s or 32Mb/s mode respectively. The last channel (Ch255 or Ch511) of the backplane output streams BSTo60 to BSTo63 or BSTo58 to BSTo63 contains invalid output data for the 16Mb/s or 32Mb/s mode respectively. Avoid using the last channel of these streams for the "local-to-backplane" data switching. The backplane connection memory determines the switching configurations. See Table 32 for the details. The "local-to-local" switching path allows users to perform data switching between the local input and the local output ports among 8,192 local input and 8,192 local output ports. The local connection memory determines the switching configurations. See Table 30 and Table 31 for the details. The "backplane-to-backplane" switching path allows users to perform data switching between the backplane input and the backplane output ports. In this switching mode, only two backplane input streams can be selected by the backplane data input selection register (BDISR). The switching capacity is 512 x 512 or 1,024 x 1,024 backplane channels for the 16Mb/s or 32Mb/s mode respectively. The BDISR register selects two backplane input data streams, namely, Stream A and Stream B to support the "backplane-to-backplane" switching. The backplane connection memory determines the switching configurations. See Table 33 for the details. 3.1 Throughput Delay The usage of the local input channel delay buffer and the local output channel advancement buffer affects the data throughput delay for the four data switching paths. The usage of these two buffers is controlled by the LICDEN and the LOCAEN bits in the control register (CR). When LICDEN and LOCAEN bits are low, the "backplane-to-local" switching path has a throughput delay of one frame plus 2 channel slots; the "local-to-backplane", the "backplaneto-backplane" and the "local-to-local" switching paths have the throughput delay of two frames. Data Delay Switching Path Input Buffer** OFF Output Buffer** OFF (LICDEN = 0) (LOCAEN = 0) Input Buffer ON Output Buffer OFF (LICDEN = 1) (LOCAEN = 0) Input Buffer OFF Output Buffer ON (LICDEN = 0) (LOCAEN = 1) Input Buffer ON Output Buffer ON (LICDEN = 1) (LOCAEN = 1) Local-to-Backplane Local-to-Local Backplane-to-Local Backplane-to-backplane 2 Frames 2 Frames 1 Frame + 2 Ch 2 Frames 3 Frames 3 Frames 1 Frame + 2 Ch 2 Frames 2 Frames 3 Frames 2 Frames + 2 Ch 2 Frames 3 Frames 4 Frames 2 Frames + 2 Ch 2 Frames ** Note: Input Buffer = Local input channel delay buffer Output Buffer = Local output channel advancement buffer. Table 2 - Data Delay Through the Device via Different Switching Paths 24 Zarlink Semiconductor Inc. Data Sheet MT90868 When the local input data streams pass through the local input channel delay buffer to perform the input channel adjustment by setting the LICDEN bit to high, the device will add one more frame data to the "local-to-backplane" and the "local-to-local" data switching paths. When the local output data streams pass through the local output channel advancement buffer to perform the output channel adjustment by setting the LOCAEN bit to high, the device will add one more frame data delay to the "backplane-to-local" and the "local-to-local" switching paths. Table 2 describes the different delay throughput for the various data switching paths. 4.0 Microprocessor Interface The MT90868 provides a microprocessor port interface for non-multiplexed bus structures. This interface is compatible to Motorola non-multiplexed bus structure specification. The required microprocessor signals are the 16-bit parallel data bus (D15 - D0), 16-bit address bus (A15 - A0) and four control lines (CS, DS, R/W and DTA). See Figure 23 for details on the Motorola non-multiplexed bus timing. The MT90868 synchronous microprocessor port provides access to the internal registers, the connection and the data memories. All memory mapping locations are read/write accessible except the local and backplane bit error rate count registers (LBCR and BBCR) and data memories which can only be read by the users. 4.1 Address Mapping of Registers and Memories The address bus of the microprocessor port interface selects the internal registers and the memories. If the address bit, A15 is low, then the registers are addressed by A14 to A0 as shown in Table 3. If A15 is high, the remaining address input lines are used to select the data and connection memory positions corresponding to the serial input or output data streams as shown in Table 4. Zarlink Semiconductor Inc. 25 MT90868 A15-A0 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H Internal Register Control Register, CR Block Programming Register, BPR Local Input Channel Delay Register 0, LICDR0 Local Input Channel Delay Register 1, LICDR1 Local Input Channel Delay Register 2, LICDR2 Local Input Channel Delay Register 3, LICDR3 Local Input Channel Delay Register 4, LICDR4 Local Input Channel Delay Register 5, LICDR5 Local Input Channel Delay Register 6, LICDR6 Local Input Channel Delay Register 7, LICDR7 Local Input Channel Delay Register 8, LICDR8 Local Input Channel Delay Register 9, LICDR9 Local Input Channel Delay Register 10, LICDR10 Local Input Channel Delay Register 11, LICDR11 Local Input Channel Delay Register 12, LICDR12 Local Input Channel Delay Register 13, LICDR13 Local Input Channel Delay Register 14, LICDR14 Local Input Channel Delay Register 15, LICDR15 Local Input Channel Delay Register 16, LICDR16 Local Input Channel Delay Register 17, LICDR17 Local Input Channel Delay Register 18, LICDR18 Local Input Channel Delay Register 19, LICDR19 Local Input Channel Delay Register 20, LICDR20 Local Input Channel Delay Register 21, LICDR21 Local Input Channel Delay Register 22, LICDR22 Local Input Channel Delay Register 23, LICDR23 Data Sheet Table 3 - Address Map for Internal Registers, when A15 = 0 26 Zarlink Semiconductor Inc. Data Sheet A15-A0 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H Internal Register Local Input Channel Delay Register 24, LICDR24 Local Input Channel Delay Register 25, LICDR25 Local Input Channel Delay Register 26, LICDR26 Local Input Channel Delay Register 27, LICDR27 Local Input Channel Delay Register 28, LICDR28 Local Input Channel Delay Register 29, LICDR29 Local Input Channel Delay Register 30, LICDR30 Local Input Channel Delay Register 31, LICDR31 Local Output Channel Advancement Register 0, LOCAR0 Local Output Channel Advancement Register 1, LOCAR1 Local Output Channel Advancement Register 2, LOCAR2 Local Output Channel Advancement Register 3, LOCAR3 Local Output Channel Advancement Register 4, LOCAR4 Local Output Channel Advancement Register 5, LOCAR5 Local Output Channel Advancement Register 6, LOCAR6 Local Output Channel Advancement Register 7, LOCAR7 Local Output Channel Advancement Register 8, LOCAR8 Local Output Channel Advancement Register 9, LOCAR9 Local Output Channel Advancement Register 10, LOCAR10 Local Output Channel Advancement Register 11, LOCAR11 Local Output Channel Advancement Register 12, LOCAR12 Local Output Channel Advancement Register 13, LOCAR13 Local Output Channel Advancement Register 14, LOCAR14 Local Output Channel Advancement Register 15, LOCAR15 Local Output Channel Advancement Register 16, LOCAR16 Local Output Channel Advancement Register 17, LOCAR17 A15-A0 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H 0049H 004AH 004BH 004CH 004DH Internal Register Local Output Channel Advancement Register 18, LOCAR18 Local Output Channel Advancement Register 19, LOCAR19 Local Output Channel Advancement Register 20, LOCAR20 Local Output Channel Advancement Register 21, LOCAR21 Local Output Channel Advancement Register 22, LOCAR22 Local Output Channel Advancement Register 23, LOCAR23 Local Output Channel Advancement Register 24, LOCAR24 Local Output Channel Advancement Register 25, LOCAR25 Local Output Channel Advancement Register 26, LOCAR26 Local Output Channel Advancement Register 27, LOCAR27 Local Output Channel Advancement Register 28, LOCAR28 Local Output Channel Advancement Register 29, LOCAR29 Local Output Channel Advancement Register 30, LOCAR30 Local Output Channel Advancement Register 31, LOCAR31 Local Input Bit Delay Register 0, LIDR0 Local Input Bit Delay Register 1, LIDR1 Local Input Bit Delay Register 2, LIDR2 Local Input Bit Delay Register 3, LIDR3 Local Input Bit Delay Register 4, LIDR4 Local Input Bit Delay Register 5, LIDR5 Local Input Bit Delay Register 6, LIDR6 Local Input Bit Delay Register 7, LIDR7 Local Input Bit Delay Register 8, LIDR8 Local Input Bit Delay Register 9, LIDR9 Local Input Bit Delay Register 10, LIDR10 Local Input Bit Delay Register 11, LIDR11 A15-A0 004EH 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH 005CH 005DH 005EH 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H MT90868 Internal Register Local Input Bit Delay Register 12, LIDR12 Local Input Bit Delay Register 13, LIDR13 Local Input Bit Delay Register 14, LIDR14 Local Input Bit Delay Register 15, LIDR15 Local Input Bit Delay Register 16, LIDR16 Local Input Bit Delay Register 17, LIDR17 Local Input Bit Delay Register 18, LIDR18 Local Input Bit Delay Register 19, LIDR19 Local Input Bit Delay Register 20, LIDR20 Local Input Bit Delay Register 21, LIDR21 Backplane Input Bit Delay Register 0, BIDR0 Backplane Input Bit Delay Register 1, BIDR1 Backplane Input Bit Delay Register 2, BIDR2 Backplane Input Bit Delay Register 3, BIDR3 Backplane Input Bit Delay Register 4, BIDR4 Backplane Input Bit Delay Register 5, BIDR5 Backplane Input Bit Delay Register 6, BIDR6 Backplane Input Bit Delay Register 7, BIDR7 Backplane Input Bit Delay Register 8, BIDR8 Backplane Input Bit Delay Register 9, BIDR9 Backplane Input Bit Delay Register 10, BIDR10 Backplane Input Bit Delay Register 11, BIDR11 Backplane Input Bit Delay Register 12, BIDR12 Backplane Input Bit Delay Register 13, BIDR13 Backplane Input Bit Delay Register 14, BIDR14 Backplane Input Bit Delay Register 15, BIDR15 Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Zarlink Semiconductor Inc. 27 MT90868 A15-A0 0068H 0069H 006AH 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0080H 0081H Internal Register Backplane Input Bit Delay Register 16, BIDR16 Backplane Input Bit Delay Register 17, BIDR17 Backplane Input Bit Delay Register 18, BIDR18 Backplane Input Bit Delay Register 19, BIDR19 Backplane Input Bit Delay Register 20, BIDR20 Backplane Input Bit Delay Register 21, BIDR21 Local Output Advancement Register 0, LOAR0 Local Output Advancement Register 1, LOAR1 Local Output Advancement Register 2, LOAR2 Local Output Advancement Register 3, LOAR3 Local Output Advancement Register 4, LOAR4 Local Output Advancement Register 5, LOAR5 Local Output Advancement Register 6, LOAR6 Local Output Advancement Register 7, LOAR7 Backplane Output Advancement Register 0, BOAR0 Backplane Output Advancement Register 1, BOAR1 Backplane Output Advancement Register 2, BOAR2 Backplane Output Advancement Register 3, BOAR3 Backplane Output Advancement Register 4, BOAR4 Backplane Output Advancement Register 5, BOAR5 Backplane Output Advancement Register 6, BOAR6 Backplane Output Advancement Register 7, BOAR7 Backplane Data Input Selection Register, BDISR Backplane Data Memory Read Selection Register, BDMRSR Local Data Memory Read Selection Register, LDMRSR Local BER Start Receive Register, LBSRR A15-A0 0082H 0083H 0084H 0085H 0086H 0087H 7FFFH Internal Register Local BER Length Register, LBLR Local BER Count Register, LBCR Backplane BER Start Receive Register, BBSRR Backplane BER Length Register, BBLR Backplane BER Count Register, BBCR Reserved Reserved Data Sheet Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) 28 Zarlink Semiconductor Inc. Data Sheet MT90868 The Control Register (CR) and the Block Programming Register (BPR) control all the major functions of the device. The Control Register (CR) and the Block Programming Register (BPR) should be programmed immediately after system power up to establish the desired switching configuration as explained in the Frame Alignment Timing and the Switching Configurations sections. The Control Register is used to select Data or Connection Memory for microport operations through the memory select bits. The register also enables the local input channel delay, the output channel advancement, the backplane per-channel output tristate or per-channel driven-high control selection, the memory block programming mode and the BER test. The Block Programming Register consists of the block programming data bits (LPBD2 - LPBD0, BBPD2 - BBPD0) and the block programming enable bit (BPE). The BPE bit allows users to program the entire backplane and local connection memories. See Memory Block Programming section. The BPR register also controls the local and the backplane frame pulse polarities. Stream Address (Stream 0 - 63) A15 (Note 1) A 14 0 0 0 0 . . . . . . 0 0 0 1 1 1 1 1 . . . . . . 1 1 1 1 A 13 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 0 . . . . . . 1 1 1 1 A 12 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 0 . . . . . . 1 1 1 1 A 11 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 1 . . . . . . 1 1 1 1 A 10 0 0 1 1 . . . . . . 0 1 1 0 0 1 1 0 . . . . . . 0 0 1 1 A 9 0 1 0 1 . . . . . . 1 0 1 0 1 0 1 0 . . . . . . 0 1 0 1 Stream # Stream 0, C or E (Note 5) Stream 1, D or F (Note 5) Stream 2 Stream 3 . . . . . . . Stream 29 Stream 30 Stream 31 Stream 32 Stream 33 Stream 34 Stream 35 Stream 36 . . . . . . Stream 60 Stream 61 Stream 62 Stream 63 A 8 0 0 0 0 . . . 0 0 0 0 0 0 0 0 . . . 0 0 0 0 1 1 . . . 1 1 A 7 0 0 0 0 . . . 0 0 0 0 1 1 1 1 . . . 1 1 1 1 0 0 . . . 1 1 A 6 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 0 1 1 0 0 . . . 1 1 Channel Address (Channel 0 - 511) A 5 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 A 4 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 A 3 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 A 2 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 A 1 0 0 1 1 . . . 0 0 1 1 0 0 1 1 . . . 0 0 1 1 0 0 . . . 1 1 A 0 0 1 0 1 . . . 0 1 0 1 0 1 0 1 . . . 0 1 0 1 0 1 . . . 0 1 Channel # Ch 0 Ch 1 Ch 2 Ch 3 . . . Ch 124 Ch 125 Ch 126 Ch 127 (Note 2) Ch 128 Ch 129 Ch 130 Ch 131 . . . Ch 252 Ch 253 Ch 254 Ch 255 (Note 3) Ch 256 Ch 257 . . . Ch 510 Ch 511 (Note 4) 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 Notes: 1. Bit A15 must be high to access the data memory and connection memory positions. (A15 must be low to access registers.) 2. Channels 0 to 127 are used when serial stream is at 8.192Mb/s. 3. Channels 0 to 255 are used when serial stream is at 16.384Mb/s. 4. Channels 0 to 511 are used when serial stream is at 32.768Mb/s. 5. Stream C&D or Stream E&F are selected by the backplane data memory read selection register (BDMRSR) or the local data memory read selection register (LDMRSR) respectively. These streams are selected to support the microprocessor port data memory read operation. Table 4 - Address Map for Memory Locations, when A15 = 1 4.2 Backplane Connection Memory The Backplane Connection Memory (BCM) is 16-bit wide. It controls the switching configuration of the backplane interface through the Backplane Source Control (BSRC) bit. When this bit is low, the input source is from the local input port and the "local-to-backplane" switching paths can be configured. When this bit is high, the input source is from the backplane input port and the "backplane-to-backplane" switching paths can be configured. Locations in the backplane connection memory are associated with particular BSTo streams. The BTM1 - BTM0 bits of each backplane connection memory determine the per-channel tristate (or driven-high) 29 Zarlink Semiconductor Inc. MT90868 control and the per-channel message and the normal modes. Data Sheet In the switching mode, the contents of the backplane connection memory stream address bits (BSAB0 - BSAB5) and channel address bits (BCAB0 - BCAB6) define the source information (stream and channel) of the time slot that will be switched to the backplane BSTo streams. During the message mode, only the lower 8 least significant bits of the backplane connection memory will be transferred to the BSTo pins. 4.3 Local Connection Memory The local connection memory controls the local interface switching configurations through the Local Mode Selection Control (LMSC) bit. When this bit is low, the input source is from the backplane input port and the "backplane-tolocal" switching path can be configured. When it is high, the input source is from the local input port and the "localto-local" switching path can be configured. The local connection memory consists of two parts, namely, the Local Connection memory Low (LCML) and the Local Connection Memory High (LCMH). Each of them is 16-bit wide. Locations in the local connection memory are associated with particular LSTo output streams. The LTM1 - LTM0 bits of each Local Connection Memory High (LCMH) determine the per-channel message mode, the pre-channel tristate and the normal modes. In the switching mode, the stream address bits (LSAB0 - LSAB5) and channel address bits (LCAB0 - LCAB8) of the local connection memory low (LCML) define the source information (stream and channel) of the time slot that will be switched to the local LSTo streams. During the message mode, only the lower 8 least significant bits of the Local Connection Memory Low are transferred to the LSTo pins. 4.4 Data Memory Read Operation All connection memory content can be read from the microprocessor port. However, only limited data memory contents can be read from the micro- processor port at any one time. The backplane data memory has 1,024 locations and the local data memory has 256 locations to support the data memory reads. The Backplane Data Memory Read Selection register (BDMRSR) selects the two backplane input streams which will be read (or monitored) from the microprocessor port. The selected backplane input streams are labelled as Stream C and Stream D. The Local Data Memory Read Selection register (LDMRSR) selects the two local input streams which will be read (or monitored) from the microprocessor port. The selected backplane input streams are labelled as Stream E and Stream F. Users need to program the BDMRSR and LDMRSR registers before the proper data memory read operations can occur. See Tables 22 and 23 for the description of the memory read selection registers. Also, see Table 4 for the microprocessor addresses required to access Stream C&D or Stream E&F. Refer to the MS0 - 2 bits in the control registers for the selection of the data memory to be read from the microprocessor port. 4.5 Data Transfer Acknowledge The DTA pin of the microprocessor is driven low by the internal logic to indicate that a data bus transfer cycle is completed. When the bus cycle is ended, the DTA switches to the high impedance state. An external pull-up is required at this output. 4.6 Local External Tristate Control The MT90868 allows users the flexibility to perform the per-channel tristate operation for the local interface when external drivers or buffers are used for the LSTo0-64 outputs. The device provides four output control signals, LCSTo0 - LCSTo3 which have the data rate of 16.384Mb/s with 8,192 control bits per frame. Each control bit position is corresponding to a specific output stream and channel location as defined in the local connection memory. When the LTM0 and LTM1 bits in the LCMH are programmed to tristate selected local output channels, the corresponding LCSTo control bits will set to high for the selected 30 Zarlink Semiconductor Inc. Data Sheet MT90868 tristate output channels. For example, if we program channel 0 of the LSTo4 to be tristated, the control bit LSTo4_Ch0 will set to high. With the local output channel advancement feature disabled, the LCSTo0 output is advanced by nine C8o cycles from the frame boundary to send out the control bit for the channel 0 of the LSTo0 stream. Similarly, the LCSTo1, LCSTo2 and LCSTo3 outputs are advanced by nine C8o cycles for the channel 0 of the LSTo1; LSTo2 and LSTo3 output streams respectively. The advancement in the LCSTo streams allows the external drivers or buffers to process the LCSTo control bits accordingly before the actual LSTo data is output from the device. FP8o C8o Ch127 Ch 0 0 7 6 5 4 3 Ch 126 2 1 0 7 6 5 Ch127 4 3 2 1 0 7 LSTo0 1 Ch127 Ch 0 0 7 6 5 4 3 Ch 126 2 1 0 7 6 5 Ch127 4 3 2 1 0 7 LSTo63 1 Nine C8o cycles LSTo24,Ch127 LSTo28,Ch127 LSTo32,Ch127 LSTo36,Ch127 LSTo40,Ch127 LSTo44,Ch127 LSTo48,Ch127 LSTo52,Ch127 LSTo56,Ch127 LSTo60,Ch127 LSTo0,Ch0 LSTo4,Ch0 LSTo8,Ch0 LSTo12,Ch0 LSTo16,Ch0 LSTo20,Ch0 LSTo24,Ch0 LSTo28,Ch0 LSTo32,Ch0 LSTo36,Ch0 LSTo40,Ch0 LSTo44,Ch0 LSTo48,Ch0 LSTo52,Ch0 LSTo56,Ch0 LSTo60,Ch0 LSTo0,Ch1 LSTo4,Ch1 LSTo8,Ch1 LST12,Ch1 LST16,Ch1 LCSTo0 LSTo56,Ch0 LSTo60,Ch0 LSTo0,Ch1 LSTo4,Ch1 LSTo8,Ch1 LSTo12,Ch1 LSTo16,Ch1 LSTo20,Ch1 LCSTo1 LSTo57,Ch0 LSTo61,Ch0 LSTo1,Ch1 LSTo5,Ch1 LSTo9,Ch1 LSTo13,Ch1 LSTo17,Ch1 LSTo21,Ch1 LCSTo2 LSTo58,Ch0 LSTo62,Ch0 LSTo2,Ch1 LSTo6,Ch1 LSTo10,Ch1 LSTo14,Ch1 LSTo18,Ch1 LSTo22,Ch1 LCSTo3 LSTo59,Ch0 LSTo63,Ch0 LSTo3,Ch1 LSTo7,Ch1 LSTo11,Ch1 LSTo15,Ch1 LSTo19,Ch1 LSTo23,Ch1 Figure 16 - Local External Tristate Control Timing When the local output channel advancement feature is enabled, LCSTo signals for those advanced output channels will also be advanced together with the actual channel outputs. Figure 16 describes the Local External Tristate Control Timing. The ODE and RESET pins also control the LCSTo pins. See Table 5, the OSB bit description in the control register. 4.7 Bit Error Rate Test The MT90868 offers users the Bit Error Rate (BER) test feature for the backplane and local interfaces. The circuitry of the BER test consists of a transmitter and a receiver on both interfaces which can transmit and receive the BER patterns independently. The transmitter can output pseudo random patterns of the form 215 - 1 which can start anywhere in the frame and last a minimum of one channel and a maximum of one frame time (125s). The BER test mode is activated by setting the LTM1 - LTM0 bits to "11" or the BTM1 - BTM0 bits to "11" in the local and the LSTo27,Ch127 LSTo31,Ch127 LSTo35,Ch127 LSTo39,Ch127 LSTo43,Ch127 LSTo47,Ch127 LSTo51,Ch127 LSTo55,Ch127 LSTo59,Ch127 LSTo63,Ch127 LSTo3,Ch0 LSTo7,Ch0 LSTo11,Ch0 LSTo15,Ch0 LSTo19,Ch0 LSTo23,Ch0 LSTo27,Ch0 LSTo31,Ch0 LSTo35,Ch0 LSTo39,Ch0 LSTo43,Ch0 LSTo47,Ch0 LSTo51,Ch0 LSTo55,Ch0 LSTo59,Ch0 LSTo63,Ch0 LSTo3,Ch1 LSTo7,Ch1 LSTo11,Ch1 LSTo15,Ch1 LSTo19,Ch1 LSTo26,Ch127 LSTo30,Ch127 LSTo34,Ch127 LSTo38,Ch127 LSTo42,Ch127 LSTo46,Ch127 LSTo50,Ch127 LSTo54,Ch127 LSTo58,Ch127 LSTo62,Ch127 LSTo2,Ch0 LSTo6,Ch0 LSTo10,Ch0 LSTo14,Ch0 LSTo18,Ch0 LSTo22,Ch0 LSTo26,Ch0 LSTo30,Ch0 LSTo34,Ch0 LSTo38,Ch0 LSTo42,Ch0 LSTo46,Ch0 LSTo50,Ch0 LSTo54,Ch0 LSTo58,Ch0 LSTo62,Ch0 LSTo2,Ch1 LSTo6,Ch1 LSTo10,Ch1 LSTo14,Ch1 LSTo18,Ch1 LSTo25,Ch127 LSTo29,Ch127 LSTo33,Ch127 LSTo37,Ch127 LSTo41,Ch127 LSTo45,Ch127 LSTo49,Ch127 LSTo53,Ch127 LSTo57,Ch127 LSTo61,Ch127 LSTo1,Ch0 LSTo5,Ch0 LSTo9,Ch0 LSTo13,Ch0 LSTo17,Ch0 LSTo21,Ch0 LSTo25Ch0 LSTo29,Ch0 LSTo33,Ch0 LSTo37,Ch0 LSTo41,Ch0 LSTo45,Ch0 LSTo49,Ch0 LSTo53,Ch0 LSTo57,Ch0 LSTo61,Ch0 LSTo1,Ch1 LSTo5,Ch1 LSTo9,Ch1 LSTo13,Ch1 LSTo17,Ch1 Zarlink Semiconductor Inc. 31 MT90868 Data Sheet backplane connection memory respectively and also setting the SBERL bit (for local) or the SBERB bit (for backplane) in the Control Register (CR) to high. For the test, the users can program the BER pattern for multiple consecutive output channels through the connection memory. However, the number of consecutive output channels must be the same as the number of input channels defined in the local and backplane BER length registers (LBLR and BBLR) which define how many BER channels to be monitored by the BER receivers. There are three types of registers to control the BER transmitter and receiver circuits. The BER Start Receive Registers for the local (LBSRR) and the backplane (BBSRR) define the input stream and channel from where the BER sequence will start to compare. The BER Length Registers for the local (LBLR) and the backplane (BBLR) define the number of input channels which the sequence will be last. The BER Count Registers for the local (LBCR) and the backplane (BBCR) contain the number of counted BER errors after the comparison. To prevent overflow, the internal BER counter will stop updating the error count when the error count reaches 0xFFFF. In additional to the BER registers, the CBERL bit and the CBERB bit of the Control Register are used to clear the backplane and the local bit error count registers; the SBERB and SBERL are used to enable the backplane and the local BER transmitters and receivers. See Table 24, 25, 26, 27, 28 and 29 for the detailed descriptions of the BER registers. The BER test should be carried out as follows: Set the SBERB and the SBERL bits to zero to disable the backplane and the local BER transmitters during the programming of the backplane and local connection memories for the BER test; when the BER transmitters are disabled, the transmitter outputs are set to zero, * Set the SBERB and SBERL bit from zero to one to enable the BER transmitters and receivers upon the completion of the programming of the connection memories, * Allow the BER transmitters and receivers to run for at least two frames (or the delay between the serial data output and the serial date input) before the BER receivers can correctly identify errors in the BER pattern but ignore the error counts displayed in the BER count registers during this training period, * After the training period, clear the BER count registers by setting the CBERL and the CBERB bit of the control register from zero to one, * Set the CBERL and CBERB bits from one to zero to release the BER counter; the BER receivers receive the BER sequence and perform the comparison, * Record the bit errors by reading the BER count registers upon the completion of the BER test, * Clear the BER counters by setting the CBERB and CBERL from zero to one upon the completion of the BER test, (Note : The transmitter and receiver for both local and backplane interface can be controlled independently to each other.) * The bit error rate test mode is available for the shaded channels. BSTo 0, 2, 4, 6, 8, 10, 12, ... , 56, 58, 60, 62. BSTo 1, 3, 5, 7, 9, 11, 13, ... , 57, 59, 61, 63. To enable the bit error rate test for the unshaded channels, one of the shaded channels on their right hand side has to be enabled. Example: To enable Ch8 for BER test mode, Ch10 or Ch11 has to be enabled. Figure 17 - Backplane Output Streams Availability for BER Test at 32Mb/s mode When the backplane port is in the 32Mb/s mode, the bit error rate test mode is not available for the backplane output streams BSTo0, 1, 4, 5, 8, 9, ... , 4n + 0 , 4n + 1 unless the output stream 4n + 2 or 4n + 3 (for 0 n 15 ) is enabled for the BER test mode. Figure 17 explains the details. When the backplane port is in the 16Mb/s mode, all backplane output streams are available. 32 Zarlink Semiconductor Inc. Data Sheet 4.8 Device Initialization MT90868 The RESET pin is a synchronous system reset signal that puts the MT90868 into its reset state. When RESET goes low, it disables the LSTo0-63 and LCSTo0-3 outputs and drives the BSTo0-63 outputs to high. It also clears the internal device registers and the internal counters. See Figure 25 for the reset timing. Upon powering up, the MT90868 must be initialized according to the following initialization sequences: * * * Set the ODE pin to low to tristate the LSTo0- 63, LCSTo0-3 and BSTo0-63 outputs. Set the TRST pin to low to disable the internal JTAG TAP controller, Set RESET pin to low to reset the device, To ensure proper reset action, the reset pin must be held low for longer than 500ns. A delay of 100s must also be applied before the first microprocessor access is performed after the RESET pin is set high, this delay is required for the initialization of the APLL. Use the Block Programming mode as described in the Memory Block Programming section to initialize the local and the backplane connection memories, Set the ODE pin to high after the connection memories are programmed to release the tristate on LSTo063, LCSTo0-3 and BSTo)-63 outputs. Set bit 11, STBY, of the Control Register (CR) to high for normal functional mode. * * * 4.9 JTAG Support The MT90868 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller. See Figure 24 for the JTAG test port timing. 4.9.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the MT90868 test functions. It consists of four input pins and one output pin as follows: * Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Input (TDi) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Output (TDo) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. Test Reset (TRST) It resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven from an external source. * * * * Zarlink Semiconductor Inc. 33 MT90868 4.9.2 Instruction Register Data Sheet The MT90868 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a fourbit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. 4.9.3 Test Data Register As specified in IEEE 1149.1, the MT90868 JTAG Interface contains three test data registers: The Boundary-Scan Register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90868 core logic. * The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDi to its TDo. * The Device Identification Register The JTAG device ID for the MT90868 is 0086814BH. Version<31:28>: 0000 Part No. <27:12>: 0000 1000 0110 1000 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: 1 * 4.9.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to support the use of the IEEE 1149 test interface. Read/Write Address: 0000H Reset Value: 0000H 15 BHIZ 14 LOCAEN 13 LICDEN 12 0 11 STBY 10 PRST 9 CBERB 8 SBERB 7 CBERL 6 SBERL 5 BMS 4 MBP 3 OSB 2 MS2 1 MS1 0 MS0 Bit 15 Name BHIZ Description Backplane Tristate or Driven-High Control: When this bit is low, the backplane outputs support the per-channel tristate feature. When this bit is high, the backplane outputs support the per-channel driven high feature. Local Output Channel Advancement Enable: When this bit is high, the Local Output Channel Advancement is enabled and the local output data will pass through the local output channel advancement buffer as shown in Figure 1. The local output channel advancement registers (LOCAR31 - LOCAR0) control the channel advancement from 0 to 127 channels. When this bit is low, the channel advancement is disabled (default condition) and the local output data will bypass the local output channel advancement buffer. Local Input Channel Delay Enable: When this bit is high, the Local Input Channel Advancement is enabled and the local input data will pass through the local input channel delay buffer as shown in Figure 1. The local input channel delay registers (LICDR31 LICDR0) control the channel delay from 0 to 127 channels. When this bit is low, the channel delay is disabled (default condition) and the local input data will bypass the local input channel delay buffer. Table 5 - Control Register (CR) Bits 14 LOCAEN 13 LICDEN 34 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 0000H Reset Value: 0000H 15 BHIZ 14 LOCAEN 13 LICDEN 12 0 11 STBY 10 PRST 9 CBERB 8 SBERB 7 CBERL 6 SBERL 5 BMS 4 MBP 3 OSB MT90868 2 MS2 1 MS1 0 MS0 Bit 12 11 10 9 Name Unused STBY PRST CBERB Description Reserved. In normal functional mode, this bit MUST be set to zero. StandBy: In normal functional mode, this bit MUST be set to one after power up. PRBS Reset: When this bit is high, the output of the BER transmitter will be initialized. Backplane Bit Error Rate Clear: When this bit is high, it resets the backplane internal bit error counter and the content of the backplane bit error count register (BBCR) to zero. Upon completion of the reset, set this bit to zero. Backplane Bit Error Rate Test Start: When this bit is high, it enables the backplane BER transmitter and receiver; starts the backplane bit error rate test. The bit error test result is kept in the backplane bit error count (BBCR) register. Upon the completion of the BER test, set this bit to zero. Local Bit Error Rate Clear: When this bit is high, it resets the local internal bit error counter and the content of the local bit error count register (LBCR) to zero. Upon completion of the reset, set this bit to zero. Local Start Bit Error Rate Test: When this bit is high, it enables the local BER transmitter and receiver; starts the local bit error rate test. The bit error test result is kept in the local bit error count (LBCR) register. Upon the completion of the BER test, set this bit to zero. Backplane Mode Select: When the BIME pin is low and this bit is low, it enables the 16Mb/s mode and BSTi0-63 and BSTo0-63 have data rate of 16.384Mb/s. When the BIME pin is low and this bit is high, it enables the 32Mb/s mode and BSTi0-63 and BSTo0-63 have data rate of 32.768Mb/s. When the BIME pin is high, set this bit to high to enable the bit interleaving mode operation. Memory Block Programming: When this bit is high, the connection memory block programming mode is enabled to program Bit 15 of the Local Connection Memory Low, Bit 0 and Bit 1 of the Local Connection Memory High and Bit 13 to Bit 15 of the Backplane Connection Memory. When it is low, the memory block programming mode is disabled. Refer to Figure 15 for details. Table 5 - Control Register (CR) Bits (continued) 8 SBERB 7 CBERL 6 SBERL 5 BMS 4 MBP Zarlink Semiconductor Inc. 35 MT90868 Read/Write Address: 0000H Reset Value: 0000H 15 BHIZ 14 LOCAEN 13 LICDEN 12 0 11 STBY 10 PRST 9 CBERB 8 SBERB 7 CBERL 6 SBERL 5 BMS 4 MBP 3 OSB Data Sheet 2 MS2 1 MS1 0 MS0 Bit 3 Name OSB Description Output Stand By Bit: This bit enables the BSTo0 - BSTOo63 and the LSTo0 - LSTo63 serial outputs. The following table describes the HiZ control of the serial data outputs: BIME Pin 1 1 1 1 0 0 0 0 0 0 RESET Pin 0 1 1 1 0 1 1 1 1 1 ODE Pin X 0 1 1 X 0 0 1 1 1 OSB Bit X X 0 1 X X X 0 0 1 BHIZ Bit X X X X X 0 1 0 1 X LSTo0 to LSTo63 HiZ HiZ HiZ Active HiZ HiZ HiZ HiZ HiZ Active BSTo0 to BSTo63 Driven High Driven High Driven High Active HiZ HiZ Driven High HiZ Driven High Active LCSTo0 to LCSTo3 Driven High Driven High Driven High Active Driven High Driven High Driven High Driven High Driven High Active 2-0 MS2 - 0 Memory Select Bit: These three bits are used to select different connection and data memories: 000, Local Connection Memory Low (LCML) is selected for read or write operations. 001, Local Connection Memory high (LCMH) is selected for read or write operations. 010, Backplane Connection Memory (BCM) is selected for read or write operations. 011, Local Data Memory is selected for read operation; Streams E and F are selected by the LDMRSR register can be read. 100, Backplane Data Memory is selected for read operation; Streams C and D are selected by the BDMRSR registers can be read. Table 5 - Control Register (CR) Bits (continued) 36 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 0001H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 LC8C 10 BFP 8C 9 LFP 16C 8 LFP 8C 7 LFP 4C 6 BBPD 2 5 BBPD 1 4 BBPD 0 3 LBPD 2 2 MT90868 1 LBPD 0 0 BPE LBPD 1 Bit 15 - 12 11 Name Unused LC8C Description Reserved. In normal functional mode, these bits MUST be set to zero. Local 8M Output (C8o) Polarity Control: When this bit is low, the C8o falling edge aligns with the frame boundary. When it is high, the C8o rising edge aligns with the frame boundary. Backplane Frame Pulse (FP8i) Polarity Control: When this bit is low, the input frame pulse should have the negative frame pulse format; the frame pulse goes low for 122ns at the frame boundary. When it is high, the input frame pulse should have the positive frame pulse format; the frame pulse goes high for 122ns at the frame boundary. Local Frame Pulse (FP16o) Polarity Control: When this bit is low, the output frame pulse has the negative frame pulse format. The frame pulse goes low for 61ns at the frame boundary. When it is high, the output frame pulse has the positive frame pulse format. The frame pulse goes high for 61ns at the frame boundary. Local Frame Pulse (FP8o) Polarity Control: When this bit is low, the output frame pulse has the negative frame pulse format. The frame pulse goes low for 122ns at the frame boundary. When it is high, the output frame pulse has the positive frame pulse format. The frame pulse goes high for 122ns at the frame boundary. Local Frame Pulse (FP4o) Polarity Control: When this bit is low, the output frame pulse has the negative frame pulse format. The frame pulse goes low for 244ns at the frame boundary. When it is high, the output frame pulse has the positive frame pulse format. The frame pulse goes high for 244ns at the frame boundary. Backplane Block Programming Data: These bits refer to the value to be loaded into the backplane connection memory (BCM) whenever the memory block programming feature is activated. After the MBP bit in the control register is set to high and the BPE bit is set to high, the contents of the bits BBPD2-0 are loaded into Bit 13 to Bit 15 of the BCM. Bit 0-12 of the BCM are zeroed. Local Block Programming Data: These bits refer to the value to be loaded into the local connection memory, i.e. Local Connection Memory Low (LCML) and Local Connection Memory High (LCMH), whenever the memory block programming feature is activated. After the MBP bit in the control register is set to high and the BPE bit is set to high, the contents of the bits LBPD0 is loaded into Bit 15 of the LCML and the LBPD1 to LBPD2 are loaded into Bit 0 to Bit 1 of the LCMH. Bit 0 to Bit 14 of LCML and Bit 2 to Bit 14 of LCMH are zeroed. Block Programming Enable.: A zero to one transition of this bit enables the memory block programming function. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must be defined in the same write operation. Once the BPE bit is set to high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to low indicating the operation is completed. When the BPE is high, the BPE or MBP can be set to low to abort the programming operation. When BPE is high, the other bits in the BPR register must not be changed for two frames to ensure a proper block programming operation. Whenever the microprocessor writes a one to the BPE bit, the block programming function is started, the user must maintain the same logical value to the other bits in the BPR register to avoid any change in the device setting. Table 6 - Block Programming Register (BPR) Bits 10 BFP8C 9 LFP16C 8 LFP8C 7 LFP4c 6-4 BBPD2 - 0 3-1 LBPD2 - 0 0 BPE Zarlink Semiconductor Inc. 37 MT90868 Read/Write Address: 0002H - 00011H Reset Value: 0000H 15 LICDR0 0 14 LICD 16 Data Sheet 13 LICD 15 12 LICD 14 11 LICD 13 10 LICD 12 9 LICD 11 8 LICD 10 7 0 6 LICD 06 5 LICD 05 4 LICD 04 3 LICD 03 2 LICD 02 1 LICD 01 0 LICD 00 LICDR1 0 LICD 36 LICD 35 LICD 34 LICD 33 LICD 32 LICD 31 LICD 30 0 LICD 26 LICD 25 LICD 24 LICD 23 LICD 22 LICD 21 LICD 20 LICDR2 0 LICD 56 LICD 55 LICD 54 LICD 53 LICD 52 LICD 51 LICD 50 0 LICD 46 LICD 45 LICD 44 LICD 43 LICD 42 LICD 41 LICD 40 LICDR3 0 LICD 76 LICD 75 LICD 74 LICD 73 LICD 72 LICD 71 LICD 70 0 LICD 66 LICD 65 LICD 64 LICD 63 LICD 62 LICD 61 LICD 60 LICDR4 0 LICD 96 LICD 95 LICD 94 LICD 93 LICD 92 LICD 91 LICD 90 0 LICD 86 LICD 85 LICD 84 LICD 83 LICD 82 LICD 81 LICD 80 LICDR5 0 LICD 116 LICD 115 LICD 114 LICD 113 LICD 112 LICD 111 LICD 110 0 LICD 106 LICD 105 LICD 104 LICD 103 LICD 102 LICD 101 LICD 100 LICDR6 0 LICD 136 LICD 135 LICD 134 LICD 133 LICD 132 LICD 131 LICD 130 0 LICD 126 LICD 125 LICD 124 LICD 123 LICD 122 LICD 121 LICD 120 LICDR7 0 LICD 156 LICD 155 LICD 154 LICD 153 LICD 152 LICD 151 LICD 150 0 LICD 146 LICD 145 LICD 144 LICD 143 LICD 142 LICD 141 LICD 140 LICDR8 0 LICD 176 LICD 175 LICD 174 LICD 173 LICD 172 LICD 171 LICD 170 0 LICD 166 LICD 165 LICD 164 LICD 163 LICD 162 LICD 161 LICD 160 LICDR9 0 LICD 196 LICD 195 LICD 194 LICD 193 LICD 192 LICD 191 LICD 190 0 LICD 186 LICD 185 LICD 184 LICD 183 LICD 182 LICD 181 LICD 180 LICDR10 0 LICD 216 LICD 215 LICD 214 LICD 213 LICD 212 LICD 211 LICD 210 0 LICD 206 LICD 205 LICD 204 LICD 203 LICD 202 LICD 201 LICD 200 LICDR11 0 LICD 236 LICD 235 LICD 234 LICD 233 LICD 232 LICD 231 LICD 230 0 LICD 226 LICD 225 LICD 224 LICD 223 LICD 222 LICD 221 LICD 220 LICDR12 0 LICD 256 LICD 255 LICD 254 LICD 253 LICD 252 LICD 251 LICD 250 0 LICD 246 LICD 245 LICD 244 LICD 243 LICD 242 LICD 241 LICD 240 LICDR13 0 LICD 276 LICD 275 LICD 274 LICD 273 LICD 272 LICD 271 LICD 270 0 LICD 266 LICD 265 LICD 264 LICD 263 LICD 262 LICD 261 LICD 260 LICDR14 0 LICD 296 LICD 295 LICD 294 LICD 293 LICD 292 LICD 291 LICD 290 0 LICD 286 LICD 285 LICD 284 LICD 283 LICD 282 LICD 281 LICD 280 LICDR15 0 LICD 316 LICD 315 LICD 314 LICD 313 LICD 312 LICD 311 LICD 310 0 LICD 306 LICD 305 LICD 304 LICD 303 LICD 302 LICD 301 LICD 300 Name LICDx6 - LICDx0 (See Note 1) Description Local Input Channel Delay Bits 6 - 0: The binary value of these seven bits defines the local input channel delay of the local data inputs. The input channel delay can be selected from Ch0 to Ch127 away from the local frame boundary. The local input channel offset delay value is only valid when the LICDEN bit is high in the control register. Note 1: x denotes a LSTi stream number from 0 to 31. Table 7 - Local Input Channel Delay Registers (LICDR0 to LICDR15) 38 Zarlink Semiconductor Inc. Data Sheet MT90868 Read/Write Address: 0012H - 00021H Reset Value: 0000H 15 LICDR16 0 14 LICD 336 13 LICD 335 12 LICD 334 11 LICD 333 10 LICD 332 9 LICD 331 8 LICD 330 7 0 6 LICD 326 5 LICD 325 4 LICD 324 3 LICD 323 2 LICD 322 1 LICD 321 0 LICD 320 LICDR17 0 LICD 356 LICD 355 LICD 354 LICD 353 LICD 352 LICD 351 LICD 350 0 LICD 346 LICD 345 LICD 344 LICD 343 LICD 342 LICD 341 LICD 340 LICDR18 0 LICD 376 LICD 375 LICD 374 LICD 373 LICD 372 LICD 371 LICD 370 0 LICD 366 LICD 365 LICD 364 LICD 363 LICD 362 LICD 361 LICD 360 LICDR19 0 LICD 396 LICD 395 LICD 394 LICD 393 LICD 392 LICD 391 LICD 390 0 LICD 386 LICD 385 LICD 384 LICD 383 LICD 382 LICD 381 LICD 380 LICDR20 0 LICD 416 LICD 415 LICD 414 LICD 413 LICD 412 LICD 411 LICD 410 0 LICD 406 LICD 405 LICD 404 LICD 403 LICD 402 LICD 401 LICD 400 LICDR21 0 LICD 436 LICD 435 LICD 434 LICD 433 LICD 432 LICD 431 LICD 430 0 LICD 426 LICD 425 LICD 424 LICD 423 LICD 422 LICD 421 LICD 420 LICDR22 0 LICD 456 LICD 455 LICD 454 LICD 453 LICD 452 LICD 451 LICD 450 0 LICD 446 LICD 445 LICD 444 LICD 443 LICD 442 LICD 441 LICD 440 LICDR23 0 LICD 476 LICD 475 LICD 474 LICD 473 LICD 472 LICD 471 LICD 470 0 LICD 466 LICD 465 LICD 464 LICD 463 LICD 462 LICD 461 LICD 460 LICDR24 0 LICD 496 LICD 495 LICD 494 LICD 493 LICD 492 LICD 491 LICD 490 0 LICD 486 LICD 485 LICD 484 LICD 483 LICD 482 LICD 481 LICD 480 LICDR25 0 LICD 516 LICD 515 LICD 514 LICD 513 LICD 512 LICD 511 LICD 510 0 LICD 506 LICD 505 LICD 504 LICD 503 LICD 502 LICD 501 LICD 500 LICDR26 0 LICD 536 LICD 535 LICD 534 LICD 533 LICD 532 LICD 531 LICD 530 0 LICD 526 LICD 525 LICD 524 LICD 523 LICD 522 LICD 521 LICD 520 LICDR27 0 LICD 556 LICD 555 LICD 554 LICD 553 LICD 552 LICD 551 LICD 550 0 LICD 546 LICD 545 LICD 544 LICD 543 LICD 542 LICD 541 LICD 540 LICDR28 0 LICD 576 LICD 575 LICD 574 LICD 573 LICD 572 LICD 571 LICD 570 0 LICD 566 LICD 565 LICD 564 LICD 563 LICD 562 LICD 561 LICD 560 LICDR29 0 LICD 596 LICD 595 LICD 594 LICD 593 LICD 592 LICD 591 LICD 590 0 LICD 586 LICD 585 LICD 584 LICD 583 LICD 582 LICD 581 LICD 580 LICDR30 0 LICD 616 LICD 615 LICD 614 LICD 613 LICD 612 LICD 611 LICD 610 0 LICD 606 LICD 605 LICD 604 LICD 603 LICD 602 LICD 601 LICD 600 LICDR31 0 LICD 636 LICD 635 LICD 634 LICD 633 LICD 632 LICD 631 LICD 630 0 LICD 626 LICD 625 LICD 624 LICD 623 LICD 622 LICD 621 LICD 620 Name LICDy6 - LICDy0 (See Note 1) Description Local Input Channel Delay Bits 6 - 0: The binary value of these seven bits defines the local input channel delay of the local data inputs. The input channel delay can be selected from Ch0 to Ch127 away from the local frame boundary. The local input channel offset delay value is only valid when the LICDEN bit is high in the control register. Note 1: y denotes a LSTi stream number from 32 to 63. Table 8 - Local Input Channel Delay Registers (LICDR16 to LICDR31) Zarlink Semiconductor Inc. 39 MT90868 Read/Write Address: 0022H - 00031H Reset Value: 0000H 15 LOCAR0 0 Data Sheet 14 LOCA 16 13 LOCA 15 12 LOCA 14 11 LOCA 13 10 LOCA 12 9 LOCA 11 8 LOCA 10 7 0 6 LOCA 06 5 LOCA 05 4 LOCA 04 3 LOCA 03 2 LOCA 02 1 LOCA 01 0 LOCA 00 LOCAR1 0 LOCA 36 LOCA 35 LOCA 34 LOCA 33 LOCA 32 LOCA 31 LOCA 30 0 LOCA 26 LOCA 25 LOCA 24 LOCA 23 LOCA 22 LOCA 21 LOCA 20 LOCAR2 0 LOCA 56 LOCA 55 LOCA 54 LOCA 53 LOCA 52 LOCA 51 LOCA 50 0 LOCA 46 LOCA 45 LOCA 44 LOCA 43 LOCA 42 LOCA 41 LOCA 40 LOCAR3 0 LOCA 76 LOCA 75 LOCA 74 LOCA 73 LOCA 72 LOCA 71 LOCA 70 0 LOCA 66 LOCA 65 LOCA 64 LOCA 63 LOCA 62 LOCA 61 LOCA 60 LOCAR4 0 LOCA 96 LOCA 95 LOCA 94 LOCA 93 LOCA 92 LOCA 91 LOCA 90 0 LOCA 86 LOCA 85 LOCA 84 LOCA 83 LOCA 82 LOCA 81 LOCA 80 LOCAR5 0 LOCA 116 LOCA 115 LOCA 114 LOCA 113 LOCA 112 LOCA 111 LOCA 110 0 LOCA 106 LOCA 105 LOCA 104 LOCA 103 LOCA 102 LOCA 101 LOCA 100 LOCAR6 0 LOCA 136 LOCA 135 LOCA 134 LOCA 133 LOCA 132 LOCA 131 LOCA 130 0 LOCA 126 LOCA 125 LOCA 124 LOCA 123 LOCA 122 LOCA 121 LOCA 120 LOCAR7 0 LOCA 156 LOCA 155 LOCA 154 LOCA 153 LOCA 152 LOCA 151 LOCA 150 0 LOCA 146 LOCA 145 LOCA 144 LOCA 143 LOCA 142 LOCA 141 LOCA 140 LOCAR8 0 LOCA 176 LOCA 175 LOCA 174 LOCA 173 LOCA 172 LOCA 171 LOCA 170 0 LOCA 166 LOCA 165 LOCA 164 LOCA 163 LOCA 162 LOCA 161 LOCA 160 LOCAR9 0 LOCA 196 LOCA 195 LOCA 194 LOCA 193 LOCA 192 LOCA 191 LOCA 190 0 LOCA 186 LOCA 185 LOCA 184 LOCA 183 LOCA 182 LOCA 181 LOCA 180 LOCAR10 0 LOCA 216 LOCA 215 LOCA 214 LOCA 213 LOCA 212 LOCA 211 LOCA 210 0 LOCA 206 LOCA 205 LOCA 204 LOCA 203 LOCA 202 LOCA 201 LOCA 200 LOCAR11 0 LOCA 236 LOCA 235 LOCA 234 LOCA 233 LOCA 232 LOCA 231 LOCA 230 0 LOCA 226 LOCA 225 LOCA 224 LOCA 223 LOCA 222 LOCA 221 LOCA 220 LOCAR12 0 LOCA 256 LOCA 255 LOCA 254 LOCA 253 LOCA 252 LOCA 251 LOCA 250 0 LOCA 246 LOCA 245 LOCA 244 LOCA 243 LOCA 242 LOCA 241 LOCA 240 LOCAR13 0 LOCA 276 LOCA 275 LOCA 274 LOCA 273 LOCA 272 LOCA 271 LOCA 270 0 LOCA 266 LOCA 265 LOCA 264 LOCA 263 LOCA 262 LOCA 261 LOCA 260 LOCAR14 0 LOCA 296 LOCA 295 LOCA 294 LOCA 293 LOCA 292 LOCA 291 LOCA 290 0 LOCA 286 LOCA 285 LOCA 284 LOCA 283 LOCA 282 LOCA 281 LOCA 280 LOCAR15 0 LOCA 316 LOCA 315 LOCA 314 LOCA 313 LOCA 312 LOCA 311 LOCA 310 0 LOCA 306 LOCA 305 LOCA 304 LOCA 303 LOCA 302 LOCA 301 LOCA 300 Name LOCAx6 - LOCAx0 (See Note 1) Description Local Output Channel Advancement Bits 6 - 0: The binary value of these seven bits defines the local output channel advancement of the local data outputs. The output channel advancement can be selected from Ch0 to Ch127 before the local frame boundary. The local output channel advancement value is only valid when the LOCAEN bit is high in the control register. Note 1: x denotes a LSTo stream number from 0 to 31. Table 9 - Local Output Channel Advancement Registers (LOCAR0 to LOCAR16) 40 Zarlink Semiconductor Inc. Data Sheet MT90868 Zarlink Semiconductor Inc. 41 MT90868 Read/Write Address: 0032H - 00041H Reset Value: 0000H 15 LOCAR16 0 Data Sheet 14 LOCA 336 13 LOCA 335 12 LOCA 334 11 LOCA 333 10 LOCA 332 9 LOCA 331 8 LOCA 330 7 0 6 LOCA 326 5 LOCA 325 4 LOCA 324 3 LOCA 323 2 LOCA 322 1 LOCA 321 0 LOCA 320 LOCAR17 0 LOCA 356 LOCA 355 LOCA 354 LOCA 353 LOCA 352 LOCA 351 LOCA 350 0 LOCA 346 LOCA 345 LOCA 344 LOCA 343 LOCA 342 LOCA 341 LOCA 340 LOCAR18 0 LOCA 376 LOCA 375 LOCA 374 LOCA 373 LOCA 372 LOCA 371 LOCA 370 0 LOCA 366 LOCA 365 LOCA 364 LOCA 363 LOCA 362 LOCA 361 LOCA 360 LOCAR19 0 LOCA 396 LOCA 395 LOCA 394 LOCA 393 LOCA 392 LOCA 391 LOCA 390 0 LOCA 386 LOCA 385 LOCA 384 LOCA 383 LOCA 382 LOCA 381 LOCA 380 LOCAR20 0 LOCA 416 LOCA 415 LOCA 414 LOCA 413 LOCA 412 LOCA 411 LOCA 410 0 LOCA 406 LOCA 405 LOCA 404 LOCA 403 LOCA 402 LOCA 401 LOCA 400 LOCAR21 0 LOCA 436 LOCA 435 LOCA 434 LOCA 433 LOCA 432 LOCA 431 LOCA 430 0 LOCA 426 LOCA 425 LOCA 424 LOCA 423 LOCA 422 LOCA 421 LOCA 420 LOCAR22 0 LOCA 456 LOCA 455 LOCA 454 LOCA 453 LOCA 452 LOCA 451 LOCA 450 0 LOCA 446 LOCA 445 LOCA 444 LOCA 443 LOCA 442 LOCA 441 LOCA 440 LOCAR23 0 LOCA 476 LOCA 475 LOCA 474 LOCA 473 LOCA 472 LOCA 471 LOCA 470 0 LOCA 466 LOCA 465 LOCA 464 LOCA 463 LOCA 462 LOCA 461 LOCA 460 LOCAR24 0 LOCA 496 LOCA 495 LOCA 494 LOCA 493 LOCA 492 LOCA 491 LOCA 490 0 LOCA 486 LOCA 485 LOCA 484 LOCA 483 LOCA 482 LOCA 481 LOCA 480 LOCAR25 0 LOCA 516 LOCA 515 LOCA 514 LOCA 513 LOCA 512 LOCA 511 LOCA 510 0 LOCA 506 LOCA 505 LOCA 504 LOCA 503 LOCA 502 LOCA 501 LOCA 500 LOCAR26 0 LOCA 536 LOCA 535 LOCA 534 LOCA 533 LOCA 532 LOCA 531 LOCA 530 0 LOCA 526 LOCA 525 LOCA 524 LOCA 523 LOCA 522 LOCA 521 LOCA 520 LOCAR27 0 LOCA 556 LOCA 555 LOCA 554 LOCA 553 LOCA 552 LOCA 551 LOCA 550 0 LOCA 546 LOCA 545 LOCA 544 LOCA 543 LOCA 542 LOCA 541 LOCA 540 LOCAR28 0 LOCA 576 LOCA 575 LOCA 574 LOCA 573 LOCA 572 LOCA 571 LOCA 570 0 LOCA 566 LOCA 565 LOCA 564 LOCA 563 LOCA 562 LOCA 561 LOCA 560 LOCAR29 0 LOCA 596 LOCA 595 LOCA 594 LOCA 593 LOCA 592 LOCA 591 LOCA 590 0 LOCA 586 LOCA 585 LOCA 584 LOCA 583 LOCA 582 LOCA 581 LOCA 580 LOCAR30 0 LOCA 616 LOCA 615 LOCA 614 LOCA 613 LOCA 612 LOCA 611 LOCA 610 0 LOCA 606 LOCA 605 LOCA 604 LOCA 603 LOCA 602 LOCA 601 LOCA 600 LOCAR31 0 LOCA 636 LOCA 635 LOCA 634 LOCA 633 LOCA 632 LOCA 631 LOCA 630 0 LOCA 626 LOCA 625 LOCA 624 LOCA 623 LOCA 622 LOCA 621 LOCA 620 Name Description LOCAy6 - LOCAy0 (See Note 1) Local Output Channel Advancement Bits 6 - 0: The binary value of these seven bits defines the local output channel advancement of the local data outputs. The output channel advancement can be selected from Ch0 to Ch127 before the local frame boundary. The local output channel advancement value is only valid when the LOCAEN bit is high in the control register. Note 1: y denotes a LSTo stream number from 32 to 63. Table 10 - Local Output Channel Advancement Registers (LOCAR15 to LOCAR31) 42 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 0042H - 00051H Reset Value: 0000H 15 LIDR0 0 MT90868 14 LID 24 LID 54 LID 84 LID 114 LID 144 LID 174 LID 204 LID 234 LID 264 LID 294 LID 324 LID 354 LID 384 LID 414 LID 444 LID 474 13 LID 23 LID 53 LID 83 LID 113 LID 143 LID 173 LID 203 LID 233 LID 263 LID 293 LID 323 LID 353 LID 383 LID 413 LID 443 LID 473 12 LID 22 LID 52 LID 82 LID 112 LID 142 LID 172 LID 202 LID 232 LID 262 LID 292 LID 322 LID 352 LID 382 LID 412 LID 442 LID 472 11 LID 21 LID 51 LID 81 LID 111 LID 141 LID 171 LID 201 LID 231 LID 261 LID 291 LID 321 LID 351 LID 381 LID 411 LID 441 LID 471 10 LID 20 LID 50 LID 80 LID 110 LID 140 LID 170 LID 200 LID 230 LID 260 LID 290 LID 320 LID 350 LID 380 LID 410 LID 440 LID 470 9 LID 14 LID 44 LID 74 LID 104 LID 134 LID 164 LID 194 LID 224 LID 254 LID 284 LID 314 LID 344 LID 374 LID 404 LID 434 LID 464 8 LID 13 LID 43 LID 73 LID 103 LID 133 LID 163 LID 193 LID 223 LID 253 LID 283 LID 313 LID 343 LID 373 LID 403 LID 433 LID 463 7 LID1 2 LID4 2 LID7 2 LID1 02 LID1 32 LID1 62 LID1 92 LID2 22 LID2 52 LID2 82 LID3 12 LID3 42 LID3 72 LID4 02 LID4 32 LID4 62 6 LID 11 LID 41 LID 71 LID 101 LID 131 LID 161 LID 191 LID 221 LID 251 LID 281 LID 311 LID 341 LID 371 LID 401 LID 431 LID 461 5 LID 10 LID 40 LID 70 LID 100 LID 130 LID 160 LID 190 LID 220 LID 250 LID 280 LID 310 LID 340 LID 370 LID 400 LID 430 LID 460 4 LID 04 LID 34 LID 64 LID 94 LID 124 LID 154 LID 184 LID 214 LID 244 LID 274 LID 304 LID 334 LID 364 LID 394 LID 424 LID 454 3 LID 03 LID 33 LID 63 LID 93 LID 123 LID 153 LID 183 LID 213 LID 243 LID 273 LID 303 LID 333 LID 363 LID 393 LID 423 LID 453 2 LID 02 LID 32 LID 62 LID 92 LID 122 LID 152 LID 182 LID 212 LID 242 LID 272 LID 302 LID 332 LID 362 LID 392 LID 422 LID 452 1 LID 01 LID 31 LID 61 LID 91 LID 121 LID 151 LID 181 LID 211 LID 241 LID 271 LID 301 LID 331 LID 361 LID 391 LID 421 LID 451 0 LID 00 LID 30 LID 60 LID 90 LID 120 LID 150 LID 180 LID 210 LID 240 LID 270 LID 300 LID 330 LID 360 LID 390 LID 420 LID 450 LIDR1 0 LIDR2 0 LIDR3 0 LIDR4 0 LIDR5 0 LIDR6 0 LIDR7 0 LIDR8 0 LIDR9 0 LIDR10 0 LIDR11 0 LIDR12 0 LIDR13 0 LIDR14 0 LIDR15 0 Name Description LIDn4 - LIDn0 (See Note 1) Local Input Bit Delay Bits 4 - 0: The binary value of these five bits defines the local input bit delay of the LSTi inputs. The local input bit delay can be selected from 0 to 7 3/4 C8o clock periods. See Table 13 for details Note 1: n denotes a LSTi stream number from 0 to 47. Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR15) Zarlink Semiconductor Inc. 43 MT90868 Read/Write Address: 0052H - 00057H Reset Value: 0000H 15 LIDR16 0 Data Sheet 14 LID 504 LID 534 LID 564 LID 594 LID 624 0 13 LID 503 LID 533 LID 563 LID 593 LID 623 0 12 LID 502 LID 532 LID 562 LID 592 LID 622 0 11 LID 501 LID 531 LID 561 LID 591 LID 621 0 10 LID 500 LID 530 LID 560 LID 590 LID 620 0 9 LID 494 LID 524 LID 554 LID 584 LID 614 0 8 LID 493 LID 523 LID 553 LID 583 LID 613 0 7 LID4 92 LID5 22 LID5 52 LID5 82 LID6 12 0 6 LID 491 LID 521 LID 551 LID 581 LID 611 0 5 LID 490 LID 520 LID 550 LID 580 LID 610 0 4 LID 484 LID 514 LID 544 LID 574 LID 604 LID 634 3 LID 483 LID 513 LID 543 LID 573 LID 603 LID 633 2 LID 482 LID 512 LID 542 LID 572 LID 602 LID 632 1 LID 481 LID 511 LID 541 LID 571 LID 601 LID 631 0 LID 480 LID 510 LID 540 LID 570 LID 600 LID 630 LIDR17 0 LIDR18 0 LIDR19 0 LIDR20 0 LIDR21 0 Name LIDn4 - LIDn0 (See Note 1) Description Local Input Bit Delay Bits 4 - 0: The binary value of these five bits defines the local input bit delay of the LSTi inputs. The local input bit delay can be selected from 0 to 7 3/4 C8o clock periods. See Table 13 for details. Note 1: n denotes a LSTi stream number from 48 to 63. Table 12 - Local Input Bit Delay Registers (LIDR16 to LIDR21) Local Input Delay C8o (period) 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 8.192Mb/s (bit) 0 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 LIDn4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Corresponding Delay Bits LIDn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 LIDn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 LIDn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LIDn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 13 - Local Input Bit Delay Programming Table 44 Zarlink Semiconductor Inc. Data Sheet Local Input Delay C8o (period) 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 8.192Mb/s (bit) 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 LIDn4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MT90868 Corresponding Delay Bits LIDn3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LIDn2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LIDn1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LIDn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 13 - Local Input Bit Delay Programming Table (continued) Zarlink Semiconductor Inc. 45 MT90868 Data Sheet Read/Write Address: 0058H - 0005DH Reset Value: 0000H 15 BIDR0 0 14 BID 24 BID 54 BID 84 BID 114 BID 144 BID 174 13 BID 23 BID 53 BID 83 BID 113 BID 143 BID 173 12 BID 22 BID 52 BID 82 BID 112 BID 142 BID 172 11 BID 21 BID 51 BID 81 BID 111 BID 141 BID 171 10 BID 20 BID 50 BID 80 BID 110 BID 140 BID 170 9 BID 14 BID 44 BID 74 BID 104 BID 134 BID 164 8 BID 13 BID 43 BID 73 BID 103 BID 133 BID 163 7 BID 12 BID 42 BID 72 BID 102 BID 132 BID 162 6 BID 11 BID 41 BID 71 BID 101 BID 131 BID 161 5 BID 10 BID 40 BID 70 BID 100 BID 130 BID 160 4 BID 04 BID 34 BID 64 BID 94 BID 124 BID 154 3 BID 03 BID 33 BID 63 BID 93 BID 123 BID 153 2 BID 02 BID 32 BID 62 BID 92 BID 122 BID 152 1 BID 01 BID 31 BID 61 BID 91 BID 121 BID 151 0 BID 00 BID 30 BID 60 BID 90 BID 120 BID 150 BIDR1 0 BIDR2 0 BIDR3 0 BIDR4 0 BIDR5 0 Name BIDn4 - BIDn0 (See Note 1) Description Backplane Input Bit Delay Bits 4 - 0: The binary value of these five bits defines the backplane input bit delay of the BSTi inputs. The backplane input bit delay can be selected from 0 to 3 7/8 C8i clock periods. See Table 16 for details. Note 1: n denotes a BSTi stream number from 0 to 17. Table 14 - Backplane Input Bit Delay Registers (BIDR0 to BIDR5) 46 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 005EH - 0006DH Reset Value: 0000H 15 BIDR6 0 MT90868 14 BID 204 BID 234 BID 264 BID 294 BID 324 BID 354 BID 384 BID 414 BID 444 BID 474 BID 504 BID 534 BID 564 BID 594 BID 624 0 13 BID 203 BID 233 BID 263 BID 293 BID 323 BID 353 BID 383 BID 413 BID 443 BID 473 BID 503 BID 533 BID 563 BID 593 BID 623 0 12 BID 202 BID 232 BID 262 BID 292 BID 322 BID 352 BID 382 BID 412 BID 442 BID 472 BID 502 BID 532 BID 562 BID 592 BID 622 0 11 BID 201 BID 231 BID 261 BID 291 BID 321 BID 351 BID 381 BID 411 BID 441 BID 471 BID 501 BID 531 BID 561 BID 591 BID 621 0 10 BID 200 BID 230 BID 260 BID 290 BID 320 BID 350 BID 380 BID 410 BID 140 BID 470 BID 500 BID 530 BID 560 BID 590 BID 620 0 9 BID 194 BID 224 BID 254 BID 284 BID 314 BID 344 BID 374 BID 404 BID 434 BID 464 BID 494 BID 524 BID 554 BID 584 BID 614 0 8 BID 193 BID 223 BID 253 BID 283 BID 313 BID 343 BID 373 BID 403 BID 433 BID 463 BID 493 BID 523 BID 553 BID 583 BID 613 0 7 BID 192 BID 222 BID 252 BID 282 BID 312 BID 342 BID 372 BID 402 BID 432 BID 462 BID 492 BID 522 BID 552 BID 582 BID 612 0 6 BID 191 BID 221 BID 251 BID 281 BID 311 BID 341 BID 371 BID 401 BID 431 BID 461 BID 491 BID 521 BID 551 BID 581 BID 611 0 5 BID 190 BID 220 BID 250 BID 280 BID 310 BID 340 BID 370 BID 400 BID 430 BID 460 BID 490 BID 520 BID 550 BID 580 BID 610 0 4 BID 184 BID 214 BID 244 BID 274 BID 304 BID 334 BID 364 BID 394 BID 424 BID 454 BID 484 BID 514 BID 544 BID 574 BID 604 BID 634 3 BID 183 BID 213 BID 243 BID 273 BID 303 BID 333 BID 363 BID 393 BID 423 BID 453 BID 483 BID 513 BID 543 BID 573 BID 603 BID 633 2 BID 182 BID 212 BID 242 BID 272 BID 302 BID 332 BID 362 BID 392 BID 422 BID 452 BID 482 BID 512 BID 542 BID 572 BID 602 BID 632 1 BID 181 BID 211 BID 241 BID 271 BID 301 BID 331 BID 361 BID 391 BID 421 BID 451 BID 481 BID 511 BID 541 BID 571 BID 601 BID 631 0 BID 180 BID 210 BID 240 BID 270 BID 300 BID 330 BID 360 BID 390 BID 420 BID 450 BID 480 BID 510 BID 540 BID 570 BID 600 BID 630 BIDR7 0 BIDR8 0 BIDR9 0 BIDR10 0 BIDR11 0 BIDR12 0 BIDR13 0 BIDR14 0 BIDR15 0 BIDR16 0 BIDR17 0 BIDR18 0 BIDR19 0 BIDR20 0 BIDR21 0 Name BIDn4 - BIDn0 (See Note 1) Description Backplane Input Bit Delay Bits 4 - 0: The binary value of these five bits defines the backplane input bit delay of the BSTi inputs. The backplane input bit delay can be selected from 0 to 3 7/8 C8i clock periods. See Table 16 for details. Note 1: n denotes a BSTi stream number from 18 to 63. Table 15 - Backplane Input Bit Delay Registers (BIDR0 to BIDR5) Zarlink Semiconductor Inc. 47 MT90868 Backplane Input Delay C8i (period) 0 (Default) 1/8 1/4 3/8 1/2 5/8 3/4 7/8 1 1 1/8 1 1/4 1 3/8 1 1/2 1 5/8 1 3/4 1 7/8 2 2 1/8 2 1/4 2 3/8 2 1/2 2 5/8 2 3/4 2 7/8 3 3 1/8 3 1/4 3 3/8 3 1/2 3 5/8 3 3/4 3 7/8 16.384Mb/s (bit) 0 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 N/A 32.768Mb/s (bit) 0 1/2 1 1 1/2 2 2 1/2 3 3 1/2 4 4 1/2 5 5 1/2 6 6 1/2 7 7 1/2 BIDn4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIDn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIDn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Data Sheet Corresponding Delay Bits BIDn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIDn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 16 - Backplane Input Bit Delay Programming Table 48 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 006EH - 00075H Reset Value: 0000H 15 LOAR0 LOA 71 MT90868 14 LOA 70 13 LOA 61 12 LOA 60 11 LOA 51 10 LOA 50 9 LOA 41 8 LOA 40 7 LOA 31 6 LOA 30 5 LOA 21 4 LOA 20 3 LOA 11 2 LOA 10 1 LOA 01 0 LOA 00 LOAR1 LOA 151 LOA 150 LOA 141 LOA 140 LOA 131 LOA 130 LOA 121 LOA 120 LOA 111 LOA 110 LOA 101 LOA 100 LOA 91 LOA 90 LOA 81 LOA 80 LOAR2 LOA 231 LOA 230 LOA 221 LOA 220 LOA 211 LOA 210 LOA 201 LOA 200 LOA 191 LOA 190 LOA 181 LOA 180 LOA 171 LOA 170 LOA 161 LOA 160 LOAR3 LOA 311 LOA 310 LOA 301 LOA 300 LOA 291 LOA 290 LOA 281 LOA 280 LOA 271 LOA 270 LOA 271 LOA 260 LOA 251 LOA 250 LOA 241 LOA 240 LOAR4 LOA 391 LOA 390 LOA 381 LOA 380 LOA 371 LOA 370 LOA 361 LOA 360 LOA 351 LOA 350 LOA 341 LOA 340 LOA 331 LOA 330 LOA 321 LOA 320 LOAR5 LOA 471 LOA 470 LOA 461 LOA 460 LOA 451 LOA 450 LOA 441 LOA 440 LOA 431 LOA 430 LOA 421 LOA 420 LOA 411 LOA 410 LOA 401 LOA 400 LOAR6 LOA 551 LOA 550 LOA 541 LOA 540 LOA 531 LOA 530 LOA 521 LOA 520 LOA 511 LOA 510 LOA 501 LOA 500 LOA 491 LOA 490 LOA 481 LOA 480 LOAR7 LOA 631 LOA 630 LOA 621 LOA 620 LOA 611 LOA 610 LOA 601 LOA 600 LOA 591 LOA 590 LOA 581 LOA 580 LOA 571 LOA 570 LOA 561 LOA 560 Name LOAn1 - LOAn0 (See Note 1) Description Local Output Advancement Bits 1 - 0: The binary value of these two bits defines the local output advancement of the LSTo outputs. The local output advancement can be selected from 0 to - 3/8 C8o clock periods. See Table 18 for details. Note 1: n denotes a LSTo stream number from 0 to 63. Table 17 - Local Output Advancement Registers (LOAR0 to LOAR7) Local Output Advancement C8o (period) 0 (Default) - 1/8 - 1/4 - 3/8 8.192Mb/s (bit) 0 - 1/8 - 1/4 - 3/8 Corresponding Advancement Bits LOAn1 0 0 1 1 LOAn0 0 1 0 1 Table 18 - Local Output Advancement Programming Table Zarlink Semiconductor Inc. 49 MT90868 Read/Write Address: 0076H - 0007DH Reset Value: 0000H 15 BOAR0 BOA 71 BOA 151 BOA 231 BOA 311 BOA 391 BOA 471 BOA 551 BOA 631 Data Sheet 14 BOA 70 BOA 150 BOA 230 BOA 310 BOA 390 BOA 470 BOA 550 BOA 630 13 BOA 61 BOA 141 BOA 221 BOA 301 BOA 381 BOA 461 BOA 541 BOA 621 12 BOA 60 BOA 140 BOA 220 BOA 300 BOA 380 BOA 460 BOA 540 BOA 620 11 BOA 51 BOA 131 BOA 211 BOA 291 BOA 371 BOA 451 BOA 531 BOA 611 10 BOA 50 BOA 130 BOA 210 BOA 290 BOA 370 BOA 450 BOA 530 BOA 610 9 BOA 41 BOA 121 BOA 201 BOA 281 BOA 361 BOA 441 BOA 521 BOA 601 8 BOA 40 BOA 120 BOA 200 BOA 280 BOA 360 BOA 440 BOA 520 BOA 600 7 BOA 31 BOA 111 BOA 191 BOA 271 BOA 351 BOA 431 BOA 511 BOA 591 6 BOA 30 BOA 110 BOA 190 BOA 270 BOA 350 BOA 430 BOA 510 BOA 590 5 BOA 21 BOA 101 BOA 181 BOA 271 BOA 341 BOA 421 BOA 501 BOA 581 4 BOA 20 BOA 100 BOA 180 BOA 260 BOA 340 BOA 420 BOA 500 BOA 580 3 BOA 11 BOA 91 BOA 171 BOA 251 BOA 331 BOA 411 BOA 491 BOA 571 2 BOA 10 BOA 90 BOA 170 BOA 250 BOA 330 BOA 410 BOA 490 BOA 570 1 BOA 01 BOA 81 BOA 161 BOA 241 BOA 321 BOA 401 BOA 481 BOA 561 0 BOA 00 BOA 80 BOA 160 BOA 240 BOA 320 BOA 400 BOA 480 BOA 560 BOAR1 BOAR2 BOAR3 BOAR4 BOAR5 BOAR6 BOAR7 Name BOAn1 - BOAn0 (See Note 1) Description Backplane Output Advancement Bits 1 - 0: The binary value of these two bits defines the backplane output advancement of the BSTo outputs. The backplane output advancement can be selected from 0 to - 3/8 C8i clock periods. See Table 20 for details. Note 1: n denotes a BSTo stream number from 0 to 63. Table 19 - Backplane Output Advancement Registers (BOAR0 to BOAR7) Backplane Output Advancement C8i (period) 0 (Default) - 1/8 - 1/4 - 3/8 16.384Mb/s (bit) 0 - 1/4 - 1/2 - 3/4 32.768Mb/s (bit) 0 - 1/2 -1 - 1 1/2 Corresponding Advancement Bits BOAn1 0 0 1 1 BOAn0 0 1 0 1 Table 20 - Backplane Output Advancement Programming Table 50 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 007EH Reset Value: 0000H 15 0 14 0 13 0 12 0 11 BDS B5 10 BDS B4 9 BDS B3 8 BDS B2 7 BDS B1 6 BDS B0 5 BDS A5 4 BDS A4 3 BDS A3 2 BDS A2 MT90868 1 BDS A1 0 BDS A0 Bit 15 - 12 11 - 6 5-0 Name Unused BDSB5 - 0 BDSA5 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Backplane Data Stream Address Bits for Stream B: The binary value of these bits refers to the backplane input data stream. Backplane Data Stream Address Bits for Stream A: The binary value of these bits refers to the backplane input data stream. Table 21 - Backplane Data Input Selection Register (BDISR) Bits Read/Write Address: 007FH Reset Value: 0000H 15 0 14 0 13 0 12 0 11 BDS D5 10 BDS D4 9 BDS D3 8 BDS D2 7 BDS D1 6 BDS D0 5 BDS C5 4 BDS C4 3 BDS C3 2 BDS C2 1 BDS C1 0 BDS C0 Bit 15 - 12 11 - 6 5-0 Name Unused BDSD5 - 0 BDSC5 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Backplane Data Stream Address Bits for Stream D: The binary value of these bits refers to the backplane input data stream. Backplane Data Stream Address Bits for Stream C: The binary value of these bits refers to the backplane input data stream. Table 22 - Backplane Data Memory Read Selection Register (BDMRSR) Bits Read/Write Address: 0080H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 LDS F5 10 LDS F4 9 LDS F3 8 LDS F2 7 LDS F1 6 LDS F0 5 LDS E5 4 LDS E4 3 LDS E3 2 LDS E2 1 LDS E1 0 LDS E0 Bit 15 - 12 11 - 6 5-0 Name Unused LDSF5 - 0 LDSE5 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Local Data Stream Address Bits for Stream F: The binary value of these bits refers to the local input data stream. Local Data Stream Address Bits for Stream E: The binary value of these bits refers to the local input data stream. Table 23 - Local Data Memory Read Selection Register (LDMRSR) Bits Zarlink Semiconductor Inc. 51 MT90868 Read/Write Address: 0081H Reset Value: 0000H 15 0 14 0 13 0 12 LBR SA5 11 LBR SA4 10 LBR SA3 9 LBR SA2 8 LBR SA1 7 LBR SA0 6 LBR CA6 5 LBR CA5 4 LBR CA4 3 LBR CA3 2 LBR CA2 Data Sheet 1 LBR CA1 0 LBR CA0 Bit 15 - 13 12 - 7 6-0 Name Unused LBRSA5 - 0 LBRCA6 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Local BER Receive Stream Address Bits: The binary value of these bits refers to the local input stream which receives the BER data. Local BER Receive Channel Address Bits: The binary value of these bits refers to the local input channel in which the BER data starts to be compared. Table 24 - Local BER Start Receiving Register (LBSRR) Bits Read/Write Address: 0082H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 LBL6 5 LBL5 4 LBL4 3 LBL3 2 LBL2 1 LBL1 0 LBL0 Bit 15 - 7 6-0 Name Unused LBL6 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Local BER Length Bits: The binary value of these bits refers to the number of channels, the BER data will last. The maximum number of local BER channels is 127. Table 25 - Local BER Length Register (LBLR) Bits Read/Write Address: 0083H Reset Value: 0000H 15 LBC 15 14 LBC 14 13 LBC 13 12 LBC 12 11 LBC 11 10 LBC 10 9 LBC 9 8 LBC 8 7 LBC 7 6 LBC 6 5 LBC 5 4 LBC 4 3 LBC 3 2 LBC 2 1 LBC 1 0 LBC 0 Bit 15 - 0 Name LBC15 - 0 Description Local Bit Error Rate Count: The binary value of these bits refers to the local bit error count. Table 26 - Local BER Count Register (LBCR) Bits 52 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 0084H Reset Value: 0000H 15 0 14 BBR SA5 13 BBR SA4 12 BBR SA3 11 BBR SA2 10 BBR SA1 9 BBR SA0 8 BBR CA8 7 BBR CA7 6 BBR CA6 5 BBR CA5 4 BBR CA4 3 BBR CA3 2 BBR CA2 MT90868 1 BBR CA1 0 BBR CA0 Bit 15 14 - 9 8-0 Name Unused BBRSA5 - 0 BBRCA8 - 0 Description Reserved. In normal functional mode, this bit MUST be set to zero. Backplane BER Receive Stream Address Bits: The binary value of these bits refers to the backplane input stream which receives the BER data. Backplane BER Receive Channel Address Bits: The binary value of these bits refers to the backplane input channel in which the BER data starts to be compared. Table 27 - Backplane BER Start Receiving Register (BBSRR) Bits Read/Write Address: 0085H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 BBL8 7 BBL7 6 BBL6 5 BBL5 4 BBL4 3 BBL3 2 BBL2 1 BBL1 0 BBL0 Bit 15 - 9 8-0 Name Unused BBL8 - 0 Description Reserved. In normal functional mode, these bits MUST be set to zero. Backplane BER Length Bits: The binary value of these bits refers to the number of channels, the BER data will last. The maximum number of backplane BER channels is 511. Table 28 - Backplane BER Length Register (BBLR) Bits Read/Write Address: 0086H Reset Value: 0000H 15 BBC 15 14 BBC 14 13 BBC 13 12 BBC 12 11 BBC 11 10 BBC 10 9 BBC 9 8 BBC 8 7 BBC 7 6 BBC 6 5 BBC 5 4 BBC 4 3 BBC 3 2 BBC 2 1 BBC 1 0 BBC 0 Bit 15 - 0 Name BBC15 - 0 Description Backplane Bit Error Rate Count: The binary value of these bits refers to the backplane bit error count. Table 29 - Backplane BER Count Register (BBCR) Bits Zarlink Semiconductor Inc. 53 MT90868 15 LMSC 14 LSAB 5 13 LSAB 4 12 LSAB 3 11 LSAB 2 10 LSAB 1 9 LSAB 0 8 LCAB 8 7 LCAB 7 6 LCAB 6 5 LCAB 5 4 LCAB 4 3 LCAB 3 2 Data Sheet 1 LCAB 1 0 LCAB 0 LCAB 2 Bit 15 Name LMSC Description Local Mode Selection Control: When this bit and the LTM0, LTM1 bits in the local connection memory high are low, the "backplane-to-local" switching is enabled. LMSC 0 LTM1 Bit in LCMH 0 LTM0 Bit in LCMH 0 Per-Channel Operation Mode 'Backplane-to-local' switching When this bit is high, the content of the LTM0, LTM1 bits in the local connection memory high select one of the operation modes described in the table below:. LMSC 1 1 1 1 LTM1 Bit in LCMH 0 0 1 1 LTM0 Bit in LCMH 0 1 0 1 Per-Channel Operation Mode 'Local-to-local switching' High Impedance Msg Mode BER Test Mode 14 - 9 8 - 0* LSAB5 - 0 LCAB8 - 0 Local Source Stream Address Bits: The binary value of these 6 bits represents the data stream number for the source (local or backplane) connection. Local Source Channel Address Bits: The binary value of these 9 bits represents the channel number that is the source (local or backplane) connection. Table 30 - Local Connection Memory low (LCML) Bits *Note: Only Bit 7-0 will be used for per-channel message mode. 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 LTM 1 0 LTM 0 Bit 15 - 2 1-0 Name Unused LTM1 - 0 Reserved. Description Local TM Bits: These two bits control the LSTo output. LTM1 0 0 0 1 1 LTM0 0 0 1 0 1 LMSC Bit in LCML 0 1 1 1 1 Per-Channel Operation Mode 'Backplane-to-local' switching 'Local-to-local' switching High Impedance Msg Mode BER Test Mode Table 31 - Local Connection Memory High (LCMH) Bits 54 Zarlink Semiconductor Inc. Data Sheet 15 BSRC =0 14 BTM 1 13 BTM 0 12 BSA B5 11 BSA B4 10 BSA B3 9 BSA B2 8 BSA B1 7 BSA B0 6 BCA B6 5 BCA B5 4 BCA B4 3 BCA B3 2 MT90868 1 BCA B1 0 BCA B0 BCA B2 Bit 15 14 - 13 Name BSRC BTM1 - 0 Description Backplane Source Control Bit: When this bit is low, the "local-to-backplane" switching is enabled and the source is from the local input port. Backplane TM Bits: These two bits control the backplane outputs. BTM1 0 0 1 1 BTM0 0 1 0 1 Per-Channel Operation Mode Normal Output Tristate/Driven-High (See Bit 15 (BHIZ) in Table 5) Msg Mode BER Test Mode 12 - 7* 6-0* BSAB5 - 0 BCAB6 - 0 Backplane Source Stream Address Bits: The binary value of these 6 bits represents the local data input stream number. Source Channel Address Bits: The binary value of these 7 bits represents the local input channel number. *Note: Only Bit 7-0 will be used for per-channel message mode. *Note: The last channel (Ch255 or Ch511) of the backplane output streams BSTo60 to BSTo63 or BSTo58 to BSTo63 contains invalid output data when operated in the 16Mb/s or 32Mb/s mode respectively. Avoid using the last channel of these streams for the "local-to-backplane" switching. Table 32 - Backplane Connection Memory (BCM) Bits for "Local-to-Backplane" Switching Zarlink Semiconductor Inc. 55 MT90868 Data Sheet 15 BSRC =1 14 BTM 1 13 BTM 0 12 0 11 0 10 0 9 BSA B0 8 BCA B8 7 BCA B7 6 BCA B6 5 BCA B5 4 BCA B4 3 BCA B3 2 BCA B2 1 BCA B1 0 BCA B0 Bit 15 14 - 13 Name BSRC BTM1 - 0 Description Backplane Source Control Bit: When this bit is high, the "backplane-to backplane" switching is enabled and the source is from the backplane input port. Backplane TM Bits: These two bits control the backplane outputs. BTM1 0 0 1 1 BTM0 0 1 0 1 Per-Channel Operation Mode Normal Output Tristate/Driven-High (See Bit 15 (BHIZ) in Table 5) Msg Mode BER Test Mode 12-10 9 Unused BSAB0 Reserved. Set to zero for normal operation. Backplane Source Stream Address Bits: When this bit is low, the source stream (Stream A) is selected. Stream A is defined in the BDISR register. When this bit is high, the source stream (Stream B) is selected. Stream B is defined in the BDISR register. Source Channel Address Bits: The binary value of these 9 bits represents the local input channel number. 8-0* BCAB8 - 0 *Note: Only Bit 7-0 will be used for per-channel message mode. Table 33 - Backplane Connection Memory (BCM) Bits for "Backplane-to-Backplane" Switching Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 Core Supply Voltage I/O Supply Voltage Input Voltage Input Voltage (5V tolerant inputs) Continuous Current at digital outputs Package power dissipation Storage temperature Symbol VDD_CORE VDD_IO VI_3V VI_5V Io PD TS - 55 Min -0.5 -0.5 -0.5 -0.5 Max 2.5 5.0 VDD + 0.5 7.0 15 2 +125 Units V V V V mA W C * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. 56 Zarlink Semiconductor Inc. Data Sheet MT90868 Characteristics Sym TOP VDD_CORE VDD_IO VI VI_5V Min -40 1.71 3.0 0 0 Typ 25 1.8 3.3 3.3 5.0 Max +85 1.89 3.6 VDD_IO 5.5 Units C V V V V Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. 1 2 3 4 5 Operating Temperature Positive Supply Positive Supply Input Voltage Input Voltage on 5V Tolerant Inputs Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 Core Supply Current 2 IO Pad Supply Current 3 Input High Voltage 4 Input Low Voltage 5 Input Leakage (input pins) Input Leakage (bi-directional pins) 6 Weak Pulldown Current for 3V tolerant input 7 Weak Pullup Current for 5V tolerant input 8 Weak Pulldown Current for 5V tolerant input 9 Input Pin Capacitance 10 Output High Voltage 11 Output Low Voltage 12 Output High Impedance Leakage 13 Output Pin Capacitance Sym IDD_CORE IDD_IO VIH VIL IIL IBL IPD_3V IPU_5V IPD_5V CI VOH VOL IOZ CO 5 2.4 0.4 5 10 2.0 0.8 5 5 50 -150 150 5 Min Typ Max 600 380 Units mA mA V V A A A A A pF V V A pF IOH = 10mA IOL = 10mA 0 < V < VDD_IO 0 AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym VCT VHM VLM Level 0.5VDD_IO 0.7VDD_IO 0.3VDD_IO Units V V V Conditions Characteristics are over recommended operating conditions unless otherwise stated. Zarlink Semiconductor Inc. 57 MT90868 AC Electrical Characteristics - Backplane and Local Clock Timing Characteristic 1 2 3 4 5 6 7 8 9 Backplane Frame Pulse Width Backplane Frame Pulse Setup Time before C8i clock falling edge Data Sheet Sym tBFPW tBFPS tBFPH tBCP tBCH tBCL trC8i, tfC8i tCVC8i tFPW4 tFOSF4 tFOHR4 tCP4 tCH4 tCL4 trC4o, tfC4o tFPW8 tFOSF8 tFOHR8 tCP8 tCH8 tCL8 trC8o, tfC8o tFPW16 tFOSF16 tFOHR16 tCP16 tCH16 tCL16 trC16o, tfC16o Min 20 10 10 120 50 50 0 0 220 110 120 239 110 110 111 50 60 119 55 55 55 20 30 59 27 27 Typ 122 Max 230 90 90 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes Backplane Frame Pulse Hold Time from C8i clock falling edge C8i Clock Period C8i Clock Pulse Width High C8i Clock Pulse Width Low C8i Clock Rise/Fall Time C8i Cycle to Cycle Variation FP4o Width from the FP4o falling edge to the C4o falling edge 122 61 61 2 2 244 122 122 244 122 122 122 61 61 122 61 61 61 30 40 61 30 30 124 70 70 3 6 270 135 145 249 135 135 7 133 75 80 125 67 67 7 67 45 50 63 33 33 7 10 FP4o Output Setup 11 FP4o Output Hold from the C4o falling edge to the FP4o rising edge CL=30pF 12 C4o Clock Period 13 C4o Clock Pulse Width High 14 C4o Clock Pulse Width Low 15 C4o Clock Rise/Fall Time 16 FP8o Width 17 FP8o Output Setup from the FP8o falling edge to the C4o falling edge 18 FP8o Output Hold from the C4o falling edge to the FP8o Rising edge 19 C8o Clock Period 20 C8o Clock Pulse Width High 21 C8o Clock Pulse Width Low 22 C8o Clock Rise/Fall Time 23 FP16o Width 24 FP16o Output Setup from the FP16o falling edge to the C4o falling edge 25 FP16o Output Hold from the C4o falling edge to the FP16o rising edge 26 C16o Clock Period 27 C16o Clock Pulse Width High 28 C16o Clock Pulse Width Low 29 C16o Clock Rise/Fall Time Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. 58 Zarlink Semiconductor Inc. Data Sheet tBFPW FP8i tBFPS tBFPH tBCP tBCH C8i tfC8i trC8i tBCL MT90868 Backplane Port Timing tFPW4 FP4o tFOSF4 tLCP4 tCH4 C4o tfC4o tFPW8 FP8o tFOSF8 tLCL8 C8o trC8o tFPW16 FP16o tCL16 C16o trC16o tfC16o tCH16 tFOSF16 tFOHR16 tLCP16 tfC8o tCH8 tFOHR8 tCP8 trC4o tCL4 tFOHR4 Local Port Timing Figure 18 - Backplane and Local Clock Timing Diagram Zarlink Semiconductor Inc. 59 MT90868 Characteristic 1 Input data sampling point for Bit 0, Bit 2, Bit 4 and Bit 6 Sym tIDS0 tIDS2 tIDS4 tIDS6 tIDS1 tIDS3 tIDS5 tIDS7 tSIS tSIH tSOD0 tSOD2 tSOD4 tSOD6 tSOD1 tSOD3 tSOD5 tSOD7 Min 106 Typ 107 Max 108 Data Sheet AC Electrical Characteristics - Backplane Data Timing for the 16Mb/s mode Units ns Notes 2 Input data sampling point for Bit 1, Bit 3, Bit 5 and Bit 7 45 46 47 ns 3 4 5 Backplane Serial Input Set-up Time Backplane Serial Input Hold Time Backplane Serial Output Delay for Bit 0, Bit 2, Bit 4 and Bit 6 3.5 1.5 68 73.5 79 ns ns ns CL=30pF 6 Backplane Serial Output Delay for Bit 1, Bit 3, Bit 5 and Bit 7 7 12.5 18 ns See Figure 19 in the next page for the 16Mb/s mode backplane data timing diagram. Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. 60 Zarlink Semiconductor Inc. Data Sheet FP8i C8i tIDS6 tIDS7 tIDS4 tIDS5 tSIS tSIH Bit0 Ch255 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit7 Ch0 Bit3 Ch0 Bit2 Ch0 tIDS2 tIDS3 BSTi0 - 63 16.384Mb/s tSOD6 tSOD7 Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 tSOD4 tSOD5 Bit4 Ch0 tSOD2 tSOD3 Bit3 Ch0 Bit2 Ch0 Figure 19 - Backplane Data Timing Diagram (16Mb/s Mode) Zarlink Semiconductor Inc. C8i 16.384Mb/s Bit2 Ch0 BSTo0 - 63 16.384Mb/s tIDS0 tIDS1 Bit1 Ch0 Bit0 Ch0 VTT tSOD0 tSOD1 BSTo0 - 63 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0 MT90868 VTT 61 MT90868 Characteristic 1 2 3 4 5 6 7 8 9 Input data sampling point for Bit 0 and Bit 4 Input data sampling point for Bit 1 and Bit 5 Input data sampling point for Bit 2 and Bit 6 Input data sampling point for Bit 3 and Bit 7 Backplane Serial Input Set-up Time Backplane Serial Input Hold Time Backplane Serial Output Delay for Bit 0 and Bit 4 Backplane Serial Output Delay for Bit 1 and Bit 5 Backplane Serial Output Delay for Bit 2 and Bit 6 Sym tIDS0 tIDS4 tIDS1 tIDS5 tIDS2 tIDS6 tIDS3 tIDS7 tSIS tSIH tSOD0 tSOD4 tSOD1 tSOD5 tSOD2 tSOD6 tSOD3 tSOD7 Min 113.5 82.6 52.3 21.8 3.5 1.5 99 69 38 8 103.5 73.5 42.5 12.5 108 78 47 17 Typ 114.5 83.6 53.3 22.8 Max 115.5 84.6 54.3 23.8 Data Sheet AC Electrical Characteristics - Backplane Data Timing for the 32Mb/s mode Units ns ns ns ns ns ns ns CL=30pF ns ns ns Notes 10 Backplane Serial Output Delay for Bit 3 and Bit 7 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. FP8i VTT C8i tIDS5 tIDS4 tIDS2 tIDS3 tIDS1 tIDS0 VTT tIDS6 tIDS7 tSIS tSIH BSTi0 - 63 32.768Mb/s Bit2 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0 VTT tSOD4 tSOD5 tSOD6 tSOD7 BSTo0 - 63 32.768Mb/s Bit2 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Bit7 Ch0 tSOD0 tSOD1 tSOD2 tSOD3 Bit3 Ch0 Bit2 Ch0 Bit1 Bit1 Ch0 Ch0 Bit0 Ch0 VTT Figure 20 - Backplane Data Timing Diagram (32Mb/s Mode) 62 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - Local Data Timing Characteristic 1 2 3 4 Input data sampling point Local Serial Input Set-up Time Local Serial Input Hold Time Local Serial Output Delay Sym tIDS tSIS tSIH tSOD Min 90 3.5 1.5 7 12.5 18 Typ 91.6 Max 94 MT90868 Units ns ns ns ns CL=30pF Notes Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. FP8o C8o tIDS tSIS tSIH LSTi0 - 63 8.192Mb/s LSTo0 - 63 8.192Mb/s Bit7 Ch127 Bit0 Ch127 Bit7 Ch0 VTT tSOD Bit7 Ch0 Bit6 Ch0 VTT Figure 21 - Local Data Timing Diagram AC Electrical Characteristics - Backplane and Local Output HiZ Timing Characteristic 1 BSTo/LSTo delay - Active to High-Z - High-Z to Active Output Driver Enable (ODE) Delay Sym tDZ, tZD tODE 13 Min Typ Max 30 25 Units ns ns Test Conditions RL=1K, CL=30pF, See Note 1 RL=1K, CL=30pF, See Note 1 2 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. C8i/C8o tDZ BSTo/LSTo Valid Data HiZ tZD BSTo/LSTo HiZ Valid Data VTT VTT ODE tODE tODE VTT VTT STo HiZ Valid Data HiZ VTT Per-Channel Tristate Timing ODE Pin Tristate Timing Figure 22 - Per-Channel and ODE Tristate Control Timing Diagrams Zarlink Semiconductor Inc. 63 MT90868 Characteristics 1 2 3 4 5 6 7 8 9 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Data hold on read Valid write data setup Sym tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tWDS tDHW tAKD tAKH 25 8 65 14 70 20 Min 0 15 5 0 5 5 4 10 10 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet AC Electrical Characteristics - Non-Multiplexed Microprocessor Port Timing Test Conditions CL=30pF CL=30pF, RL=1K Note 1 10 Data hold on write 11 Acknowledgment Delay 12 Acknowledgment Hold Time CL=30pF CL=30pF, RL=1K, Note 1 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8V and VDD_IO at 3.3V and are for design aid only: not guaranteed and not subject to production testing. Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. DS tCSS CS tRWS R/W tADS A0-A15 VALID ADDRESS VTT tCSH VTT tRWH VTT tADH VTT tDHR D0-D15 READ tWDS D0-D15 WRITE VALID READ DATA VTT tDHW VALID WRITE DATA VTT tDDR DTA tAKD tAKH VTT Figure 23 - Motorola Non-Multiplexed Bus Timing 64 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW tRSTW 200 500 Min 200 80 80 10 10 20 90 30 Typ Max MT90868 Units ns ns ns ns ns ns ns ns ns ns CL=30pF CL=30pF CL=30pF Notes 10 Reset pulse width Characteristics are over recommended operating conditions unless otherwise stated. tTCKL TCK tTCKH tTCKP tTMSS TMS tTMSH tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST Figure 24 - JTAG Test Port Timing Diagram tRSTW Reset Figure 25 - Reset Pin Timing Diagram Zarlink Semiconductor Inc. 65 Figure 26 - Bit Interleaving Mode Timing Diagram for Backplane Input and Output Streams Ch509 Bit0 Ch510 Bit0 Ch511 Bit0 Ch0 Bit7 Ch1 Bit7 Ch2 Bit7 Ch3 Bit7 Ch0 Bit6 Ch1 Bit6 Ch2 Bit6 Ch3 Bit6 Ch0 Bit5 Ch1 Bit5 Ch2 Bit5 Ch3 Bit5 Ch0 Bit4 Ch1 Bit4 Ch2 Bit4 Ch3 Bit4 Ch0 Bit3 Ch1 Bit3 Ch2 Bit3 Ch3 Bit3 Ch0 Bit2 Ch1 Bit2 Ch2 Bit2 Ch3 Bit2 Ch0 Bit1 Ch1 Bit1 Ch2 Bit1 Ch3 Bit1 Ch0 Bit0 Ch1 Bit0 Ch2 Bit0 Ch3 Bit0 Ch4 Bit7 Ch5 Bit7 Ch6 Bit7 Ch7 Bit7 Ch4 Bit6 Ch5 Bit6 Ch6 Bit6 Ch7 Bit6 Ch4 Bit5 Ch5 Bit5 Ch6 Bit5 Ch7 Bit5 Ch4 Bit4 Ch5 Bit4 Ch6 Bit4 Ch7 Bit4 Data Sheet BSTo0-63 (32Mb/s) Bit Interleaving Ch511 Bit1 Ch508 Bit0 Ch509 Bit0 Ch510 Bit0 Ch511 Bit0 Ch0 Bit7 Ch1 Bit7 Ch2 Bit7 Ch3 Bit7 Ch0 Bit6 Ch1 Bit6 Ch2 Bit6 Ch3 Bit6 Ch0 Bit5 Ch1 Bit5 Ch2 Bit5 Ch3 Bit5 Ch0 Bit4 Ch1 Bit4 Ch2 Bit4 Ch3 Bit4 Ch0 Bit3 Ch1 Bit3 Ch2 Bit3 Ch3 Bit3 Ch0 Bit2 Ch1 Bit2 Ch2 Bit2 Ch3 Bit2 Ch0 Bit1 Ch1 Bit1 Ch2 Bit1 Ch3 Bit1 Ch0 Bit0 Ch1 Bit0 Ch2 Bit0 Ch3 Bit0 Ch4 Bit7 Ch5 Bit7 Ch6 Bit7 Ch7 Bit7 Ch4 Bit6 Ch5 Bit6 Ch6 Bit6 Ch7 Bit6 Ch4 Bit5 Ch5 Bit5 Ch6 Bit5 Ch7 Bit5 Ch4 Bit4 Ch5 Bit4 Ch6 Bit4 66 MT90868 APPENDIX - Bit Interleaving Mode When the bit interleaving mode is selected for the backplane port, the delay between the frame pulse signals is six 32Mb/s channels plus 10 cycles of C8i. See Figure 27 for the frame pulse offset timing in the bit interleaving mode. When the device is in the bit interleaving mode, the bit error rate test feature is not available for the backplane port BSTi0 - 63 and BSTo0 - 63. The bit interleaving mode performs the bit grooming function for the backplane input and output streams which have data rate of 32Mb/s. This mode is enabled by setting the bit interleaving mode enable (BIME) pin to one. The bit shuffling is performed for every four-channel as indicated in FIgure 26. The input delay and the output advancement shown in FIgure 26 are realized by programming the backplane input delay registers (LIDR0 to LIDR21) and the backplane output advancement registers (BOAR0 to BOAR7) as described in Table 11 & 12 and Table 20 respectively. FP8i (8kHz) C8i (8.192MHz) Channel 511 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Zarlink Semiconductor Inc. TS 127 Timeslot 0 Output Stream advanced by -1/4 C8i by programming the BOAR registers Timeslot 0 BSTi0-63/STo0-63 (32Mb/s) No Bit Interleaving 3210765432107654321076543210765432107654321076543210 Input Stream delayed by 1/4 C8i by programming the BIDR registers Timeslot 1 BSTi0-63 (32Mb/s) Bit Interleaving Timeslot 1 Data Sheet 11 (32Mb/s) channels FP8i C8i TS127 Time Slot 0 Time Slot 1 Time Slot 2 BSTi/BSTo0-63 (32Mb/s) FP8o C8o Channel 125 7 6 5 6 5 4 3 4 2 1 7 0 Channel 126 3 2 1 0 7 6 5 Channel 127 4 3 2 1 0 7 Channel 0 6 5 4 Figure 27 - Backplane and Local Frame Pulse Alignment Diagram for the Bit Interleaving Mode Zarlink Semiconductor Inc. LSTi/LSTo0-63 (8Mb/s) MT90868 67 Package Code Previous package codes For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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